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10 hoursMerge branch 'next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git # Conflicts: # Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
10 hoursMerge branch 'usb-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git # Conflicts: # drivers/thunderbolt/tb.c
7 daysdt-bindings: phy: tegra194: Add compatible for Tegra238Jon Hunter
The Tegra238 XUSB pad controller is similar to that found on the Tegra194 and Tegra234, but only has three USB2 ports and three USB3 ports. Add the Tegra238 compatible string for the XUSB pad controller and constrain the binding so that a Tegra238 device tree can only have three USB2 and three USB3 ports. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20261007-tegra-phy-v3-1-d501de414710@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
11 daysdt-bindings: phy: aspeed: Document AST2700 USB3.2 PHYRyan Chen
Document AST2700 USB3.2 PHY. This IP is connected between USB3 controller and PHY module. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://patch.msgid.link/20260916-upstream_usb3phy-v4-1-812e76037d01@aspeedtech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
11 daysdt-bindings: phy: rockchip-inno-csi-dphy: add rk3576 variantAmin Gattout
The Rockchip RK3576 features two MIPI CSI-2 DPHYs compatible with this binding. Unlike the RK3588 variant, each PHY instance only has an APB reset line, so add the new compatible to the single-reset group as well. No fallback compatible is used because the RK3576 DPHYs match neither existing variant: their control bits sit in a dedicated CSI-DPHY GRF as on RK3588 (rather than in the shared VI GRF used on RK3568), while only a single APB reset is wired up, as on RK3568. Falling back to "rockchip,rk3588-csi-dphy" would make the driver request a second, non-existent reset, and falling back to "rockchip,rk3568-csi-dphy" would make it write to the wrong GRF offsets, so dedicated match data is required. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Amin Gattout <amin.gattout@gmail.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Michael Riesch <michael.riesch@collabora.com> Link: https://patch.msgid.link/20260915-rk3576-dphy-v2-2-b56e68b54b8c@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
11 daysdt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHYAngeloGioacchino Del Regno
This adds bindings for the PCI-Express Gen4 S-PHY found in newer MediaTek SoCs, such as MT8196 and its variants. In the current "revision 3", depending on the specific port, this S-PHY supports up to two lanes of PCI-Express Gen 4 and both EP and RC modes. It is not clear whether revisions/versions earlier than 3 have ever been shipped in any other MediaTek SoC. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20260915101022.23852-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
11 daysdt-bindings: phy: Add nvidia,tegra264-mphyKartik Rajput
Add binding for the MIPI M-PHY on NVIDIA Tegra264 SoCs. The M-PHY is a hardware block with two lanes, l0 and l1, used by the Tegra264 UFS host controller. Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260909-tegra264-mphy-v1-1-ce61a80dc065@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
12 daysdt-bindings: phy: tegra-xusb: Add support for Tegra264Wayne Chang
Add the compatible string for the Tegra264 XUSB PHY. A dedicated compatible string is used instead of falling back to nvidia,tegra234-xusb-padctl, because Tegra264 is not programming-compatible with Tegra234, even though they share the same DT property set. The driver selects per-SoC data from the compatible string, and Tegra264 differs from Tegra234 in at least: - Tegra264 uses hardware tracking mode (trk_hw_mode), while Tegra234 disables it. - On Tegra234, CYA_TRK_CODE_UPDATE_ON_IDLE needs to be cleared so that the calibration values can be captured while the controller is still in reset. Tegra264 does not require this, and the corresponding handling is not even present for it. A fallback of nvidia,tegra234-xusb-padctl would let an OS that only knows about Tegra234 probe Tegra264 with the wrong programming sequence. This is also why Tegra234 did not fall back to nvidia,tegra194-xusb-padctl in this same binding: the DT schema is shared, but each generation needs its own compatible. Signed-off-by: Wayne Chang <waynec@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260903071937.533646-2-waynec@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
12 daysdt-bindings: phy: mediatek,xsphy: add optional repeater phys propertyJulien Massot
USB2 PHY ports may be connected to an external eUSB2 repeater chip. Add an optional phys property to the port sub-node to allow referencing it, following the same pattern used by the Synopsys eUSB2 PHY binding. Signed-off-by: Julien Massot <julien.massot@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20260826-mtk-usb2-repeater-usb2-v1-1-e8e48e2fd6d8@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: ti,tcan104x-can: Document Microchip MCP2542Stefan Wahren
The Microchip MCP2542 High-speed CAN transceiver with Sleep mode is a pin-compatible alternative for the TI TCAN1042. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260907150420.18787-4-wahrenst@gmx.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document the Nord QMP PHYBartosz Golaszewski
Add a compatible for the USB3+DP combo QMP PHY found on the Qualcomm Nord SoC. The PHY sits behind a GDSC, so also allow (and require) power-domains for it. The block gets a standalone compatible rather than a fallback to an existing one, because it is not register-compatible with any PHY already described here. Its USB3 and DP initialisation sequences do match sm8550, but Nord places the sub-blocks at different offsets within the PHY: it exposes a dedicated USB3_PCS_AON region at 0x1e00, which sm8550 does not have at all. Falling back to sm8550 - or to any other entry - would make the driver program the wrong addresses. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Assisted-by: LLM Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260921-nord-usb-phy-v3-2-68aa02b12b96@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: qcom,snps-eusb2-phy: Document the Nord eUSB2 PHYBartosz Golaszewski
Add a compatible for the eUSB2 PHY found on the Qualcomm Nord SoC. It is compatible with the sm8550 eUSB2 PHY. While at it: On Nord SoC there are three eUSB2 PHYs but only two QUSB2PHY block resets: the HS-only USB20 tile has no dedicated PHY reset and is instead reset as a whole through the controller's own USB20_PRIM_BCR. Make the 'resets' property optional for qcom,nord-snps-eusb2-phy only, keeping it required for all the other compatibles. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260921-nord-usb-phy-v3-1-68aa02b12b96@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: qcom: add Nord QMP PCIe PHY bindingKrishna Chaitanya Chundru
Document the PCIe PHY found on the Qualcomm Nord platform. Nord has a 32.0 GT/s capable QMP PCIe PHY that can operate in multiple lane configurations using four PHY segments (A/B/C/D). The active topology is selected by firmware through a TCSR configuration register and may be configured as x16, x8+x8, x8+x4+x4, or x8+x4+x2+x2. The binding describes the register regions, clocks, resets, power domains, regulators, PHY provider interface, clock provider interface, and the qcom,link-mode property used by the driver to discover the active lane configuration programmed by firmware. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20260921-nord-v4-1-ed05c6e09240@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Maili PCIe PHY compatiblesVivek Pernamitta
Add qcom,maili-qmp-gen3x2-pcie-phy and qcom,maili-qmp-gen4x1-pcie-phy compatible strings for the Maili SoC PCIe QMP PHY. Maili reuses the Hawi QMP PCIe PHY hardware, so the compatibles use the two-item fallback format with Hawi as the fallback: qcom,maili-qmp-gen3x2-pcie-phy -> qcom,hawi-qmp-gen3x2-pcie-phy qcom,maili-qmp-gen4x1-pcie-phy -> qcom,hawi-qmp-gen4x1-pcie-phy Since the allOf conditions use 'contains:' to match against the compatible array, and Maili nodes always carry the Hawi fallback string as the second compatible. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-vdev_next-20260916_dt-v4-1-e2f22f67646e@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible for ↵Nitin Rawat
Maili Document the QMP UFS PHY compatible for Qualcomm Maili to support physical layer functionality for UFS found on the SoC. Use fallback to indicate the compatibility of the QMP UFS PHY on the Maili with that on the Hawi. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com> Link: https://patch.msgid.link/20260917080622.824253-1-nitin.rawat@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
13 daysdt-bindings: phy: rockchip-usbdp: add improved ports schemeSebastian Reichel
Currently the Rockchip USBDP PHY is missing a documented port scheme. Meanwhile upstream RK3588 DTS files are a bit messy and use different port schemes. The upstream USBDP PHY Linux kernel driver does not yet parse the ports at all and thus does not create any implicit ABI either. But with the current mess it is not possible to properly support USB-C DP AltMode. Thus this introduces a proper port scheme following roughly the ports design of the Qualcomm QMP USB4-USB3-DP PHY controller binding with a slight difference that there is an additional port for the USB-C SBU port as the Rockchip USB-DP PHY also contains the SBU mux. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://patch.msgid.link/20260915-rockchip-usbdp-cleanup-v15-1-80e2c11d1ce8@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-29dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Glymur compatibleNihal Kumar Gupta
Glymur integrates the same CSI2 PHY IP as X1E80100. Add qcom,glymur-csi2-phy falling back to qcom,x1e80100-csi2-phy. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
2026-09-23dt-bindings: phy: ti,tcan104x-can: Fix property constrainsStefan Wahren
Microchip ATA6561 is compatible to TI TCAN1042, so the same property constrains should apply. But they use a strict scalar enum match, which makes Microchip ATA6561 fallthrough. So add a "contains" to cover also all compatibles ones. Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/linux-devicetree/20260902133525.E22DE1F000E9@smtp.kernel.org/ Fixes: 05ace63d0bcf ("dt-bindings: phy: ti,tcan104x-can: Document NXP TJA105X/1048") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260907150420.18787-2-wahrenst@gmx.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-23Merge branch 'topic/phy_qcom_camss' into nextVinod Koul
2026-09-23dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schemaBryan O'Donoghue
Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. This PHY supports both DPHY and CPHY operation. A special mode of DPHY operation - called variously split-mode or combo-mode also allows for two sensors to be connected to one PHY. The schema supports both the D-PHY and C-PHY bus types. Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-x1e-csi2-phy-v18-1-6515b5255fa9@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-23dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schemaBryan O'Donoghue
Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. This PHY supports both DPHY and CPHY operation. A special mode of DPHY operation - called variously split-mode or combo-mode also allows for two sensors to be connected to one PHY. The schema supports both the D-PHY and C-PHY bus types. Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-x1e-csi2-phy-v18-1-6515b5255fa9@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-15dt-bindings: phy: qcom,qmp-usb3-dp: Extend X1E description for USB4Konrad Dybcio
Some instances of the QMP combo PHY (called USB43DP) feature a third functional sub-block, responsible for USB4/Thunderbolt 3 communication. Compared to the today's state of the binding, one more clock (P2RR2P - PHY-to-Router, Router-to-PHY) needs to be enabled for the PHY to be able to switch to USB4 mode. Allow that for X1E. Also, add a bindings define to let consumers access it. Assisted-by: Claude:sonnet-5 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260908-topic-usb4phy-v5-1-73aac69578ef@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-15dt-bindings: phy: mediatek,tphy: Add support for MT8189 SoCLouis-Alexis Eyraud
Add a compatible string for the MediaTek MT8189 SoC, that integrates a MediaTek generic T-PHY version 3. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20260701-mt8189-dt-bindings-tphy-v1-1-5848a2be8303@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-15dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Maili QMP PhyKrishna Kurapati
Document the QMP PHY for Maili which handles the USB3 path. Use fallback to indicate the compatibility of the QMP PHY on Maili with that on Hawi. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260817-maili-usb-v2-2-97d7317f64b3@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-15dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for MailiKrishna Kurapati
Document the M31 eUSB2 PHY for Maili which handles the USB2 path. Use fallback to indicate the compatibility of the M31 eUSB2 PHY on Maili with that on the SM8750. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260817-maili-usb-v2-1-97d7317f64b3@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-15dt-bindings: phy: sc8280xp-qmp-pcie: Document Shikra PCIe phySushrut Shree Trivedi
Document the compatible of the Shikra PCIe phy which supports Gen2x1. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260831-shikra-upstream-v2-1-406661d75afa@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-15dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYsAngeloGioacchino Del Regno
This adds bindings for the DisplayPort and Embedded DisplayPort PHYs found in the MediaTek MT8195 SoC (and variants of) and for the Embedded DisplayPort found in the MT8196 SoC (and variants). This PHY supports varying impedance calibrations for the various signals to reach an optimal EYE signal pattern for any specific board(s), especially useful for very high bitrates such as HBR3 and higher, depending on board design. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20260910092038.48291-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-10dt-bindings: phy: ti,am335x-usb-phy: Convert to DT schemaBhargav Joshi
Convert the TI AM335x USB PHY text bindings to DT schema. Add undocumented vcc-supply property to match existing DTS usage. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260901-ti-am33-usb-v3-2-5e15c617d2e9@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-08-24Merge tag 'phy-for-7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "As usual bunch of new device and driver support and updates to existing drivers and addition of Manivannan to help with reviews. New Support: - Mediatek MT8196 DSI PHY support - Renesas RZ/G3L usb2 support - Qualcomm SM8475 QMP USB PHY and PCIe phy, IPQ9650 QMP PCIe PHY, QUSB2 Phy for Shikra SoC, Hawi support for QMP PCIe phy and UFS PHY. Glymur QMP PCIe Multi-PHY driver and multiple link-mode support, ipq5210 PCIe phy support - Spacemit USB3/PCIe comb PHY driver Updates: - Samsung hdptx driver improvements for modernizing the register access and code cleanup - Qualcomm drop duplicate v8 DP headers, improved runtime handling for qmp drivers - Rockchip clock lane phase tuning and 2500 Mbps support and TMDS rate handling - Freescale imx8mq improvements for runtime pm, pd handling" * tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (76 commits) MAINTAINERS: Add Manivannan Sadhasivam as the Reviewer for Generic PHY Framework phy: rockchip-samsung-dcphy: fix out-of-range max_register phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY phy: rockchip: samsung-hdptx: Consistently use bitfield macros phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling phy: rockchip: samsung-hdptx: Consolidate consumer_put on error path phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL phy: rockchip: samsung-hdptx: Guard against clk rate integer underflow phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy phy: qcom: qmp-combo: Correct pre-emphasis table for QMP v4 DP PHYs phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY ...
2026-08-11dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHYQiang Yu
Add qcom,glymur-qmp-gen5x8-pcie-phy.yaml as a standalone binding for the Glymur Gen5 PCIe PHY hardware block. This block supports two link modes, selected at runtime via a TCSR syscon register: 1. x8 - a single 8-lane PHY instance is exposed 2. x4+x4 - two independent 4-lane PHY instances are exposed Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml rather than folding it into the shared compatible list there, since the two PHY instances active in x8 mode require twice as many clocks, resets, and power-domains as any other entry in that file, and adding Glymur-specific properties like qcom,link-mode and reg-names there would only apply to this one compatible. Document the required clocks, resets, and power-domains for both PHY instances, and use #phy-cells = <1>, where the cell value is the PHY index within the active link mode. Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-1-dd1c7e236e29@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-07dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHYEsteban Urrutia
SM8450 init sequence for this PHY varies significantly and can't be reused in SM8475. Add bindings for the PHY found in this SoC. Signed-off-by: Esteban Urrutia <esteuwu@proton.me> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-1-48bd91a19abf@proton.me Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-07dt-bindings: phy: qcom,sa8775p-dwmac-sgmii-phy: add named voltage rails and ↵Mohd Ayaan Anwar
deprecate phy-supply The Qualcomm SGMII SerDes PHY has two distinct voltage supply rails, vdda-0p9 and vdda-1p2. The binding incorrectly described only a single generic supply via 'phy-supply'. Deprecate 'phy-supply' and instead add two named supply properties. The 0.9V rail draws a peak current of 46 mA and the 1.2V rail draws 15 mA. Fixes: 97b795125704 ("dt-bindings: phy: describe the Qualcomm SGMII PHY") Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-b4-sgmiieth_serdes_regulator-v2-1-c4bc688177dd@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-07dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add Hawi UFS PHY compatiblePalash Kambar
Document QMP UFS PHY compatible for Hawi SoC. Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Palash Kambar <palash.kambar@oss.qualcomm.com> Link: https://patch.msgid.link/20260806161301.1010876-2-palash.kambar@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase propertyGerald Loacker
Add support for the optional rockchip,clk-lane-phase device tree property to allow board-specific tuning of the clock lane sampling phase for improved signal integrity across supported data rates. Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Michael Riesch <michael.riesch@collabora.com> Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net> Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHYEsteban Urrutia
SM8450 init sequence for this PHY varies significantly and can't be used in SM8475. Add bindings for the PHY found in this SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Esteban Urrutia <esteuwu@proton.me> Link: https://patch.msgid.link/20260804-sm8475-bup-usbss-v3-1-9a5b9ebf62de@proton.me Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06dt-bindings: phy: renesas,usb2-phy: Document RZ/G3L PHY bindingsBiju Das
Add device tree binding support for the RZ/G3L (r9a08g046) USB2 PHY. The RZ/G3L USB PHY is almost identical to the RZ/G3S USB PHY, the difference being 2 OTG blocks on RZ/G3L compared to 1 on RZ/G3S. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260806102236.149159-7-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for HawiRonak Raheja
Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi with that on the SM8750. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260803091441.3040830-3-mukesh.ojha@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHYRonak Raheja
Document the Hawi compatible string for the QMP combo PHY. Hawi uses a new QSERDES V10 register layout with a new COM AON module and hardware-specific PHY init sequences compared to previous targets, requiring a dedicated compatible string. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260803091441.3040830-2-mukesh.ojha@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22dt-bindings: phy: qcom,ipq8074-qmp-pcie: document IPQ9650 QMP PCIe PHYsKathiravan Thirumoorthy
Document the single-lane and dual-lane QMP PCIe PHYs found on the IPQ9650 SoC. Unlike the PHYs in the other supported IPQ SoCs, the IPQ9650 PHYs require the on-chip refgen supply to power up. Add the refgen-supply property and require it only for the IPQ9650 compatibles. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://patch.msgid.link/20260710-ipq9650_pcie_phy-v3-1-ef6018818d33@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the ipq5210 QMP PCIe PHYVaradarajan Narayanan
The ipq5210 has one dual lane and one single lane PCIe phy. The dual lane phy is similar to the dual lane phy present in ipq9574. Hence qcom,ipq5210-qmp-gen3x2-pcie-phy is documented with ipq9574's dual lane phy as fallback compatible. The single lane phy (qcom,ipq5210-qmp-gen3x1-pcie-phy) is documented as specific compatible as it uses a combination of its own initialization tables and some of the existing tables. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://patch.msgid.link/20260721-pcie-phy-v5-1-8d403ef7e780@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22dt-bindings: phy: qcs615-qmp-usb3dp: Add support for Shikra SoCKrishna Kurapati
Declare the USB-C QMP PHY present on the Qualcomm Shikra SoC. Shikra uses 3 resets to be programmed before initialising the phy. As per the hardware documentation, the third reset is PHY_PRIM_SP0_BCR, hence naming it "phy". Also, add remote endpoints and orientation switch support for getting Type-C orientation information. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260712-usb-shikra-phy-v6-v6-2-1b3e51bf1541@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22dt-bindings: phy: qcom,qusb2: Document QUSB2 Phy for ShikraKrishna Kurapati
Update dt-bindings to add Shikra to QUSB2 Phy list. Shikra SoC has two High Speed QUSB2 Phys. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://patch.msgid.link/20260712-usb-shikra-phy-v6-v6-1-1b3e51bf1541@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20dt-bindings: phy: mediatek,dsi-phy: Add support for MT8196AngeloGioacchino Del Regno
Add support for the MediaTek Kompanio Ultra (MT8196) SoC: this chip features a DSI PHY that is similar to the one found in the MT8183 SoC, but is a new (incremental) revision with a different register layout. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20260713103805.23030-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy supportInochi Amaoto
The USB3/PCIe comb PHY on the K3 is a complex PHY group that can provide multiple phy for both PCIe and USB controller. Its mux configuration is controlled by the APMU syscon device. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260703021024.495433-2-inochiama@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Hawi compatiblesMatthew Leung
Document the compatibles for the Gen3 x2 and Gen4 x1 QMP PCIe PHYs found on the Hawi platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-1-8d9cc6324947@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-30dt-bindings: Drop incorrect usage of double '::'Krzysztof Kozlowski
There is no use of double colon '::' in YAML. OTOH, the literal style block, e.g. using '|' treats all characters as content [1] therefore single use of ':' in descriptions is perfectly fine, whenever '|' is used. Cleanup existing code, so the confusing style won't be re-used in new contributions. Link: https://yaml.org/spec/1.2.2/#literal-style [1] Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20260623054842.21831-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-23Merge tag 'phy-for-7.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Bunch of new driver, device support in existing drivers/binding and few updates to existing drivers New Support: - Qualcomm Eliza QMP PHY, Eliza Synopsys eUSB2 support, Eliza PCIe phy support, Nord QMP UFS PHY, IPQ5210 USB3 PHY support - Econet EN751221 and EN7528 PCIe phy support - NXPs TJA1145 CAN transceiver phy support - TI DS125DF111 retimer phy support - Rockchip RK3528 usb phy support - TI J722S phy support - Axiado eMMC PHY driver - EyeQ5 Ethernet PHY driver - Generic PHY driver for Lynx 10G SerDes - Spacemit K3 USB2 PHY support Updates: - Tomi helping maintian zynqmp phys - lynx phy updates to support 25GBASER - Rockchip GRF for RK3568/RV1108 support - Qualcomm QSERDES COM v2 support" * tag 'phy-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (87 commits) phy: rockchip: inno-usb2: Add missing clkout_ctl_phy kerneldoc phy: Move MODULE_DEVICE_TABLE next to the table itself phy: add basic support for NXPs TJA1145 CAN transceiver dt-bindings: phy: add support for NXPs TJA1145 CAN transceiver phy: freescale: phy-fsl-imx8qm-lvds-phy: Fix missing pm_runtime_disable() on probe error path dt-bindings: phy: qcom,qmp-usb: Add ipq5210 USB3 PHY dt-bindings: phy: qcom,qusb2: Document IPQ5210 compatible phy: freescale: phy-fsl-imx8qm-lvds-phy: Use synchronous PM runtime put in reset MAINTAINERS: expand Lynx 28G entry to cover Lynx 10G SerDes phy: lynx-10g: new driver dt-bindings: phy: lynx-10g: initial document phy: lynx-28g: improve phy_validate() procedure phy: lynx-28g: optimize read-modify-write operation phy: lynx-28g: add support for big endian register maps phy: lynx-28g: common probe() and remove() phy: lynx-28g: make lynx_28g_pll_read_configuration() callable per PLL phy: lynx-28g: move struct lynx_info definitions downwards phy: lynx-28g: provide default lynx_lane_supports_mode() implementation phy: lynx-28g: generalize protocol converter accessors phy: lynx-28g: common lynx_pll_get() ...
2026-06-11dt-bindings: phy: add support for NXPs TJA1145 CAN transceiverDimitri Fedrau
Adding documentation for NXPs TJA1145 CAN transceiver, which resides like the ti,tcan104x-can.yaml in the same directory as other generic PHY subsystem bindings. At the moment there is only support for simple PHYs by using regulator bindings in combination with can-transceiver.yaml or PHYs that implement the generic PHY subsystem like the NXP TJA1145. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com> Link: https://patch.msgid.link/20260602-tja1145-support-v6-1-0e0ffc8ee63d@liebherr.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: qcom,qmp-usb: Add ipq5210 USB3 PHYVaradarajan Narayanan
Add dt-bindings for the USB3 QMP PHY found on the Qualcomm IPQ5210 SoC. The IPQ5210 PHY is compatible with the IPQ9574 PHY, so add it as a fallback- compatible entry using a oneOf construct rather than a plain enum entry. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260608103344.2740174-3-varadarajan.narayanan@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: phy: qcom,qusb2: Document IPQ5210 compatibleVaradarajan Narayanan
Document the QUSB2 PHY compatible for the IPQ5210 SoC. The IPQ5210 PHY is compatible with the IPQ6018 QUSB2 PHY, so allow it to use qcom,ipq6018-qusb2-phy as the fallback compatible. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260608103344.2740174-2-varadarajan.narayanan@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>