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5 daysdt-bindings: renesas,rcar-dmac: Add support for R-Car X5H SoCWolfram Sang
Also add the familiy compatible because X5H is the first R-Car Gen5 SoC. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260909094009.2167-9-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
7 daysdt-bindings: dma: dma40: Restore disabled-channelsLinus Walleij
The conversion of the DMA40 binding to YAML omitted the optional disabled-channels property from the original text binding. The driver still parses this property, but additionalProperties: false rejects any device tree using it. Restore disabled-channels and constrain it to the physical channel range. Also constrain memcpy-channels to the limits enforced by the driver and reject duplicate channel entries in both properties. Fixes: 23fbc87c8ae6 ("dt-bindings: dma: Rewrite ST-Ericsson DMA40 to YAML") Assisted-by: LLM Signed-off-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260918-dma40-dt-disabled-channels-v1-1-0f691109d8d3@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
8 daysdt-bindings: dma: qcom,gpi: Document the Nord GPI DMA engineBartosz Golaszewski
Add the compatible string for the GPI DMA engine found on the Nord family of SoCs. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-nord-gpi-dt-bindings-v1-1-857bf9e84999@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
8 daysdt-bindings: dma: Convert hisilicon,k3-dma-1.0 to DT schemaRob Herring (Arm)
Convert the hisilicon,k3-dma-1.0 binding to DT schema format. Add dma-channel-mask, dma-no-cci, dma-type and interrupt-names properties which were not documented. The "hisilicon,hisi-pcm-asp-dma-1.0" doesn't have clocks, so make it optional. Assisted-by: LLM Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Link: https://patch.msgid.link/20260928124448.3754740-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
8 daysdt-bindings: dma: Add Amlogic A9 SoC DMAXianwei Zhao
Add documentation describing the Amlogic A9 SoC DMA. And add the properties specific values defines into a new include file. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://patch.msgid.link/20260903-amlogic-dma-v12-1-f769bc344056@amlogic.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
8 daysdt-bindings: dma: qcom,gpi: Document GPI DMA engine for MailiJyothi Kumar Seerapu
Document the GPI DMA engine on the Maili platform. Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Acked-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260901-maili_gpi_binding-v2-1-c10dd2324a09@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
8 daysdt-bindings: dmaengine: sun50i-a64-dma: Add allwinner,sun60i-a733-dma ↵Yuanshen Cao
compatible string Add `allwinner,sun60i-a733-dma` to the list of compatible strings for the `sun50i-a64-dma` dtbinding documentation. While the A733 DMA controller shares many similarities with the sun50i-a64 DMA controller, it requires a specific configuration due to differences in: - Interrupt register layout and mapping. - Number of channels per interrupt register. - Support for higher (32G) address widths in LLI parameters. Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yuanshen Cao <alex.caoys@gmail.com> Link: https://patch.msgid.link/20260826-sun60i-a733-dma-v5-4-abc5229b441e@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
8 daysdt-bindings: dma: mediatek,uart-dma: add mt6572Roman Vivchar
Add a compatible string for the mt6572 APDMA, that is compatible with mt6577 IP. Signed-off-by: Roman Vivchar <rva333@protonmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20260914-6572-dt-uartdma-v1-1-b26b429ab68c@protonmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-09dt-bindings: dma: ti,cppi41: Convert to DT schemaBhargav Joshi
Convert TI CPPI 4.1 DMA controller text bindings to DT schema. Add ti,am3359-cppi41 and ti,da830-cppi41 into single schema since they share the same hardware IP block and driver. Add undocumented #dma-requests and power-domains properties to match existing DTS usage. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260901-ti-am33-usb-v3-1-5e15c617d2e9@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-09dt-bindings: dma: ti,dma-crossbar: Convert to DT schemaBhargav Joshi
Convert Texas Instruments DMA Crossbar from text to DT schema. Modify MAINTAINERS file to correctly point to new yaml file. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260825-ti-dma-crossbar-v4-1-b0bc78cf071e@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-09dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatibleJia Wang
The DP1000 integrates a DMA controller. Add its SoC-specific compatible with the generic fallback. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260907-ultrarisc-dts-v2-7-5eb4c97477c5@ultrarisc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-09-09dt-bindings: dma: apple,admac: Add M3 generation ADMACsSasha Finkelstein
The admacs seen in M3-generation SoCs (t603x, t8122) need additional configuration writes and so are getting a new compatible chain. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Joshua Peisach <jpeisach@ubuntu.com> Reviewed-by: Janne Grunau <j@jannau.net> Signed-off-by: Sasha Finkelstein <k@chaosmail.tech> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260815-t603x-admac-v4-1-1149e342dcb0@chaosmail.tech Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-14dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to 7Kuldeep Singh
Qualcomm Shikra platform describes the BAM DMA node with 7 iommus entries. The current schema limit to 6, so update the binding to allow up to 7 entries. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Link: https://patch.msgid.link/20260714-b4-shikra_crypto_changse-v4-5-06a4ea97c209@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-08MAINTAINERS: replace maintainer for Altera mSGDMA driverAdrian Ng Ho Yin
Olivier Dautricourt has stepped down as maintainer of the Altera msgDMA driver as he no longer has access to the hardware. Replace him with Adrian Ng Ho Yin as the new maintainer and update the status from "Odd Fixes" to "Maintained". Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/addaf51275355667045ec300fc8d725e2e273807.1782911845.git.adrian.ho.yin.ng@altera.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-02dt-bindings: dma: mediatek,uart-dma: add support for MT8189 SoCLouis-Alexis Eyraud
Add the compatible string for the APDMA IP found in MT8189 SoC, that supports 35-bits addressing as MT6985 SoC. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260701-mt8189-dt-bindings-uart-dma-v1-1-c7106216a40d@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-01dt-bindings: dma: xilinx: Fix "xlnx,irq-delay" typeRob Herring (Arm)
"xlnx,irq-delay" programs an 8-bit delay field in the DMA control register, and the driver stores and reads it as a byte. The binding described the property as a uint32 cell, which made the helper type check report the driver as wrong. Document "xlnx,irq-delay" as uint8 so the generated schema reflects the hardware field width and the existing driver access. Assisted-by: Codex:gpt-5-5 Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://patch.msgid.link/20260612215226.1887726-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-01dt-bindings: dma: xlnx,axi-dma: Restore xlnx,flush-fsync as u32Suraj Gupta
The DT schema conversion incorrectly changed xlnx,flush-fsync from a u32 property to a boolean. The original binding documented values 1, 2, and 3 to select which VDMA channel(s) flush on frame sync. Restore the uint32 type with the documented enum values and fix the example accordingly. Fixes: 2d5c2952b972 ("dt-bindings: dma: xlnx,axi-dma: Convert to DT schema") Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260625161016.1249570-1-suraj.gupta2@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-23Merge tag 'dmaengine-7.2-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "Core: - New devm_of_dma_controller_register() API - Refactor devm_dma_request_chan() API New Support: - Loongson Multi-Channel DMA controller support - Renesas RZ/{T2H,N2H} support - Dw CV1800B DMA support - Switchtec DMA engine driver U pdates: - Xilinx AXI dma binding conversion - Renesas CHCTRL register read updates - AMD MDB Endpoint and non-LL mode Support - AXI dma handling of SW and HW cyclic transfers termination - Intel ioatdma and idxd driver updates" * tag 'dmaengine-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (62 commits) dt-bindings: dma: snps,dw-axi-dmac: Add fallback compatible for CV1800B MAINTAINERS: dmaengine/ti: Remove myself and add Vignesh as maintainer dmaengine: qcom: Unify user-visible "Qualcomm" name dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC dmaengine: qcom: hidma: use sysfs_emit() in sysfs show callbacks dmaengine: dw-axi-dmac: fix PM for system sleep and channel alloc dmaengine: dw-axi-dmac: drop redundant DMAC enable in block start dmaengine: altera-msgdma: Use memcpy_toio for descriptor FIFO writes dt-bindings: dma: fsl-edma: add dma-channel-mask property description dmaengine: tegra: Fix burst size calculation dmaengine: iop32x-adma: Remove a leftover header file dmaengine: dma-axi-dmac: use DMA pool to manange DMA descriptor dmaengine: dma-axi-dmac: Drop struct clk from main struct dmaengine: dma-axi-dmac: Properly free struct axi_dmac_desc dmaengine: Fix possible use after free dmaengine: dw-edma: Add spinlock to protect DONE_INT_MASK and ABORT_INT_MASK dmaengine: dw-edma-pcie: Reject devices without driver data dmaengine: sh: rz-dmac: Add DMA ACK signal routing support irqchip/renesas-rzv2h: Add DMA ACK signal routing support dmaengine: dw-edma: Remove dw_edma_add_irq_mask() ...
2026-06-11dt-bindings: dma: snps,dw-axi-dmac: Add fallback compatible for CV1800BInochi Amaoto
The previous version of the binding change only add compatible string without adding the fallback compatible, this breaks backward compatibility. Add the needed fallback compatible to fix this. Fixes: be3e2a0419c6 ("dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatible") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260511063818.463877-2-inochiama@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoCXueyao An
Document the GPI DMA engine on Shikra platform. It is fully compatible with the GPI DMA engine found on SM6350, thus using qcom,sm6350-gpi-dma as fallback compatible. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://patch.msgid.link/20260608-shikra-dt-m1-v4-1-2114300594a6@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11dt-bindings: dma: fsl-edma: add dma-channel-mask property descriptionJoy Zou
Add documentation for the dma-channel-mask property in the fsl-edma binding. This property uses an inverted bit definition: bit value 0 indicates the channel is available, while bit value 1 indicates unavailable. That was already used widely for i.MX8, i.MX9. Correcting the definition will break backward compatibility. This reversal only impacts the eDMA dts node and driver, and doesn't impact DMA consumer. Therefore, keep the inverted definition. Also add a note at the top of the binding to highlight this inverted definition to prevent confusion. Signed-off-by: Joy Zou <joy.zou@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260211-b4-imx95-v2x-v4-1-10852754b267@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-04dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map propertyAkhil R
Add iommu-map property to specify separate stream IDs for each DMA channel. This enables each channel to be in its own IOMMU domain, keeping memory isolated from other devices sharing the same DMA controller. Define the constraints such that if the channel and stream IDs are contiguous, a single entry can map all the channels, but if the channels or stream IDs are non-contiguous support multiple entries. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260331102303.33181-4-akhilrajeev@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-04dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optionalAkhil R
On Tegra264, GPCDMA reset control is not exposed to Linux and is handled by the boot firmware. Although reset was not exposed in Tegra234 as well, the firmware supported a dummy reset which just returns success on reset without doing an actual reset. This is also not supported in Tegra264 BPMP. Therefore mark 'reset' and 'reset-names' properties as required only for devices prior to Tegra264. This also necessitates that the Tegra264 compatible be standalone and cannot have the fallback compatible of Tegra186. Since there is no functional impact, we keep reset as required for Tegra234 to avoid breaking the ABI. Fixes: bb8c97571db5 ("dt-bindings: dma: Add Tegra264 compatible string") Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260331102303.33181-2-akhilrajeev@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-19dt-bindings: dma: qcom,gpi: Document the Eliza GPI DMA engineAbel Vesa
Document the GPI DMA engine found on the Eliza SoC. It is fully compatible with the GPI DMA engine found on SM6350, thus using qcom,sm6350-gpi-dma as fallback compatible. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://patch.msgid.link/20260515-eliza-gpi-dma-v2-1-1255b43d5ca9@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-19dt-bindings: dmaengine: Add SpacemiT K3 DMA compatible stringGuodong Xu
Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. While the K3 PDMA IP reuses most of the design found on the earlier K1 SoC, a new compatible string is required because the DRCMR (DMA Request/Command Register) base address for extended DMA request numbers (>= 64) differs from the K1 implementation. Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://patch.msgid.link/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-19dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Hawi SoCXueyao An
The Hawi GPI DMA engine follows the same programming model and register interface as previous generation of Qualcomm SoCs like kaanapali, glymur, and is fully compatible with earlier GPI DMA implementations. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260401124028.589931-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-19dt-bindings: dma: qcom,bam-dma: Document BAM v2.0.0 compatibleKuldeep Singh
Document compatible string for bam v2.0.0 version found on kaanapali. BAM v2.0.0 differs from the earlier v1.7.X revision in terms of register layout and offsets, requiring a distinct compatible for correct hardware description. Also add a new example for BAM v2.0.0 to illustrate a more complete configuration than the existing v1.4 example. The new example covers 64-bit address and size cells, IOMMU bindings and execution environment–related properties required on newer platforms. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260514-knp_qce-v2-1-890e3372eef8@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-15dt-bindings: Consolidate "sram" property definitionRob Herring (Arm)
The "sram" property has become a de facto standard property, so create a common schema for it and drop all the duplicated definitions. Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Jakub Kicinski <kuba@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Liu Ying <victor.liu@nxp.com> #fsl,imx8qxp-dc-command-sequencer.yaml Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> # display/msm Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Tanmay Shah <tanmay.shah@amd.com> Link: https://patch.msgid.link/20260511165942.2774868-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-03-18dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson"Colin Ian King
There is a spelling mistake in the title field. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Reviewed-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://patch.msgid.link/20260317204938.120729-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controllerBinbin Zhou
The Loongson-2K0300/Loongson-2K3000 have built-in multi-channel DMA controllers, which are similar except for some of the register offsets and number of channels. Obviously, this is quite different from the APB DMA controller used in the Loongson-2K0500/Loongson-2K1000, such as the latter being a single-channel DMA controller. To avoid cluttering a single dt-binding file, add a new yaml file. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/135802de72b84f643d0b0624f3f79f13777147a1.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dt-bindings: dma: xlnx,axi-dma: Convert to DT schemaAbin Joseph
Convert the bindings document for Xilinx DMA. No changes to existing binding description. Signed-off-by: Abin Joseph <abin.joseph@amd.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260309033444.3472359-1-abin.joseph@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3LBiju Das
The RZ/G3L DMA controller is compatible with RZ/G2L, sharing the same IP. However, the conditional schema logic that enforces RZ/G2L-specific binding constraints was not extended to cover the RZ/G3L compatible string, leaving its bindings without proper validation. Add the RZ/G3L compatible string to the existing RZ/G2L conditional schema so that the same property constraints are applied to both SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Fixes: e45cf0c7d9b960f1 ("dt-bindings: dma: rz-dmac: Document RZ/G3L SoC") Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260306145819.897047-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}Cosmin Tanislav
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three DMAC instances. Compared to the previously supported RZ/V2H, these SoCs are missing the error interrupt line and the reset lines, and they use a different ICU IP. Document them, and use RZ/T2H as a fallback for RZ/N2H as the DMACs are entirely compatible. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260105114445.878262-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-26dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatibleInochi Amaoto
The DMA controller on CV1800B needs to use the DMA phandle args as the channel number instead of hardware handshake number, so add a new compatible for the DMA controller on CV1800B. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260120013706.436742-2-inochiama@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-25dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent propertyKhairul Anuar Romli
The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller operates on a cache-coherent AXI interface, where DMA transactions are automatically kept coherent with the CPU caches. In previous generations SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there is no need for dma-coherent property to be presence. In Agilex 5, the architecture has changed. It introduced a coherent interconnect that supports cache-coherent DMA. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://patch.msgid.link/20260131172856.29227-1-dinguyen@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-25dt-bindings: dma: rz-dmac: Document RZ/G3L SoCBiju Das
Document the Renesas RZ/G3L DMAC block. This is identical to the one found on the RZ/G3S SoC. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260203103031.247435-2-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-17Merge tag 'dmaengine-7.0-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "Core: - Add Frank Li as susbstem reviewer to help with reviews New Support: - Mediatek support for Dimensity 6300 and 9200 controller - Qualcomm Kaanapali and Glymur GPI DMA engine - Synopsis DW AXI Agilex5 - Renesas RZ/V2N SoC - Atmel microchip lan9691-dma - Tegra ADMA tegra264 Updates: - sg_nents_for_dma() helper use in subsystem - pm_runtime_mark_last_busy() redundant call update for subsystem - Residue support for xilinx AXIDMA driver - Intel Max SGL Size Support and capabilities for DSA3.0 - AXI dma larger than 32bits address support" * tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (64 commits) dmaengine: add Frank Li as reviewer dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16 dmaengine: fsl-edma: don't explicitly disable clocks in .remove() dmaengine: xilinx: xdma: use sg_nents_for_dma() helper dmaengine: sh: use sg_nents_for_dma() helper dmaengine: sa11x0: use sg_nents_for_dma() helper dmaengine: qcom: bam_dma: use sg_nents_for_dma() helper dmaengine: qcom: adm: use sg_nents_for_dma() helper dmaengine: pxa-dma: use sg_nents_for_dma() helper dmaengine: lgm: use sg_nents_for_dma() helper dmaengine: k3dma: use sg_nents_for_dma() helper dmaengine: dw-axi-dmac: use sg_nents_for_dma() helper dmaengine: bcm2835-dma: use sg_nents_for_dma() helper dmaengine: axi-dmac: use sg_nents_for_dma() helper dmaengine: altera-msgdma: use sg_nents_for_dma() helper scatterlist: introduce sg_nents_for_dma() helper dmaengine: idxd: Add Max SGL Size Support for DSA3.0 dmaengine: idxd: Expose DSA3.0 capabilities through sysfs dmaengine: sh: rz-dmac: Make channel irq local dmaengine: pl08x: Fix comment stating the difference between PL080 and PL081 ...
2026-02-04dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16Pankaj Patil
Update interrupt maxItems to 16 from 13 per GPI instance to support Glymur, Qualcomm's latest gen SoC Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251231133114.2752822-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-28Merge tag 'tegra-for-6.20-dt-bindings-v2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Changes for v6.20-rc1 This series updates various DT bindings for Tegra architecture, primarily focusing on schema validation fixes and new feature documentation for Tegra234 and Tegra264 SoCs. Key changes include converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock support). Additionally, it resolves legacy warnings for Tegra30/132 display and VI interfaces. * tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: display: tegra: document Tegra30 VI and VIP dt-bindings: display: tegra: document Tegra132 MIPI calibration device dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema dt-bindings: dma: Update ADMA bindings for tegra264 dt-bindings: iommu: Add NVIDIA Tegra CMDQV support dt-bindings: memory: tegra: Document DBB clock for Tegra264 dt-bindings: tegra: pmc: Update aotag as an optional aperture
2026-01-16dt-bindings: dma: Update ADMA bindings for tegra264sheetal
- Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-01dt-bindings: dma: atmel: add microchip,lan9691-dmaRobert Marko
Document Microchip LAN969x DMA compatible which is compatible to SAMA7G5. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229184004.571837-10-robert.marko@sartura.hr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5Khairul Anuar Romli
The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask. Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/dbc775f114445c06c6e4ce424333e1f3cbb92583.1766966955.git.khairul.anuar.romli@altera.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: dma: pl08x: Do not use plural form of a proper noun PrimeCellVladimir Zapolskiy
As a proper noun PrimeCell is a single entity and it can not have a plural form, fix the typo. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251225181519.1401953-1-vz@mleia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: Update ADMA bindings for tegra264sheetal
- Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20250929105930.1767294-2-sheetal@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Kaanapali and Glymur ↵Jyothi Kumar Seerapu
SoCs Document the GPI DMA engine on the Kaanapali and Glymur platforms. Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251105-knp-bus-v2-1-ed3095c7013a@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: mediatek,uart-dma: Support all SoC generationsAngeloGioacchino Del Regno
Add support for the APDMA IP found in all of the SoC generations that are currently supported upstream; this includes: - MT8173, MT8183, fully compatible with MT6577 (32-bits) - MT7988, MT8186, MT8188, MT8192, MT8195 and MT6835 (34-bits) - MT6991, MT8196 and MT6985 (35-bits) ...where: - MT6835 is the first SoC where the AP_DMA IP supports 34-bits addressing; and - MT6985 is the first SoC where the AP_DMA IP supports 35-bits addressing. While at it, also add myself in the maintainers list. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-4-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: mediatek,uart-dma: Deprecate mediatek,dma-33bitsAngeloGioacchino Del Regno
While this property wants to express a capability of the hardware, this is only used by the driver itself to vary the DMA bits during probe. Different hardware shall instead have different compatible strings. Following the driver cleanup and the introduction of a specific compatible string for the APDMA IP version found in MT6795, set the "mediatek,dma-33bits" vendor property as deprecated. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-3-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: mediatek,uart-dma: Allow MT6795 single compatibleAngeloGioacchino Del Regno
While it is true that this SoC is compatible with the MT6577 APDMA IP, that is valid only when the IP is used in 32-bits addressing mode, and, by the way there is no good reason to do so. Since the APDMA IP in MT6795 supports 33 bits addressing, this means that it is a newer revision compared to the one found in MT6577, hence only partially compatible with it. Allow nodes to specify "mediatek,mt6795-uart-dma" as their only compatible in the case of MT6795; this is done in lieu of the fact that there are other SoCs integrating the same version of this IP as MT6795, and those will eventually get their own compatible that expresses full compatibility with this SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dt-bindings: Updates Linus Walleij's mail addressLinus Walleij
My name is stamped into maintainership for a big slew of DT bindings. Now that it is changing, switch it over to my kernel.org mail address, which will hopefully be stable for the rest of my life. Signed-off-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20251216-maintainers-dt-v1-1-0b5ab102c9bb@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-16dt-bindings: dma: rz-dmac: Document RZ/V2N SoC supportLad Prabhakar
Document the DMA controller on the Renesas RZ/V2N SoC, which is architecturally identical to the DMAC found on the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125212621.267397-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>