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-rw-r--r--rust/kernel/auxiliary.rs30
-rw-r--r--rust/kernel/debugfs.rs86
-rw-r--r--rust/kernel/debugfs/callback_adapters.rs21
-rw-r--r--rust/kernel/debugfs/entry.rs14
-rw-r--r--rust/kernel/debugfs/file_ops.rs43
-rw-r--r--rust/kernel/debugfs/traits.rs43
-rw-r--r--rust/kernel/device.rs32
-rw-r--r--rust/kernel/device/property.rs11
-rw-r--r--rust/kernel/devres.rs197
-rw-r--r--rust/kernel/dma.rs17
-rw-r--r--rust/kernel/driver.rs12
-rw-r--r--rust/kernel/faux.rs13
-rw-r--r--rust/kernel/io.rs479
-rw-r--r--rust/kernel/io/mem.rs33
-rw-r--r--rust/kernel/io/poll.rs16
-rw-r--r--rust/kernel/irq/request.rs6
-rw-r--r--rust/kernel/lib.rs2
-rw-r--r--rust/kernel/pci.rs11
-rw-r--r--rust/kernel/pci/id.rs2
-rw-r--r--rust/kernel/pci/io.rs210
-rw-r--r--rust/kernel/platform.rs46
-rw-r--r--rust/kernel/scatterlist.rs3
-rw-r--r--rust/kernel/soc.rs135
23 files changed, 1116 insertions, 346 deletions
diff --git a/rust/kernel/auxiliary.rs b/rust/kernel/auxiliary.rs
index be76f11aecb7..93c0db1f6655 100644
--- a/rust/kernel/auxiliary.rs
+++ b/rust/kernel/auxiliary.rs
@@ -5,19 +5,30 @@
//! C header: [`include/linux/auxiliary_bus.h`](srctree/include/linux/auxiliary_bus.h)
use crate::{
- bindings, container_of, device,
- device_id::{RawDeviceId, RawDeviceIdIndex},
+ bindings,
+ container_of,
+ device,
+ device_id::{
+ RawDeviceId,
+ RawDeviceIdIndex, //
+ },
devres::Devres,
driver,
- error::{from_result, to_result, Result},
+ error::{
+ from_result,
+ to_result, //
+ },
prelude::*,
types::Opaque,
- ThisModule,
+ ThisModule, //
};
use core::{
marker::PhantomData,
mem::offset_of,
- ptr::{addr_of_mut, NonNull},
+ ptr::{
+ addr_of_mut,
+ NonNull, //
+ },
};
/// An adapter for the registration of auxiliary drivers.
@@ -90,7 +101,7 @@ impl<T: Driver + 'static> Adapter<T> {
// SAFETY: The auxiliary bus only ever calls the probe callback with a valid pointer to a
// `struct auxiliary_device`.
//
- // INVARIANT: `adev` is valid for the duration of `probe_callback()`.
+ // INVARIANT: `adev` is valid for the duration of `remove_callback()`.
let adev = unsafe { &*adev.cast::<Device<device::CoreInternal>>() };
// SAFETY: `remove_callback` is only ever called after a successful call to
@@ -121,12 +132,7 @@ impl DeviceId {
let name = name.to_bytes_with_nul();
let modname = modname.to_bytes_with_nul();
- // TODO: Replace with `bindings::auxiliary_device_id::default()` once stabilized for
- // `const`.
- //
- // SAFETY: FFI type is valid to be zero-initialized.
- let mut id: bindings::auxiliary_device_id = unsafe { core::mem::zeroed() };
-
+ let mut id: bindings::auxiliary_device_id = pin_init::zeroed();
let mut i = 0;
while i < modname.len() {
id.name[i] = modname[i];
diff --git a/rust/kernel/debugfs.rs b/rust/kernel/debugfs.rs
index facad81e8290..d7b8014a6474 100644
--- a/rust/kernel/debugfs.rs
+++ b/rust/kernel/debugfs.rs
@@ -8,28 +8,52 @@
// When DebugFS is disabled, many parameters are dead. Linting for this isn't helpful.
#![cfg_attr(not(CONFIG_DEBUG_FS), allow(unused_variables))]
-use crate::fmt;
-use crate::prelude::*;
-use crate::str::CStr;
#[cfg(CONFIG_DEBUG_FS)]
use crate::sync::Arc;
-use crate::uaccess::UserSliceReader;
-use core::marker::PhantomData;
-use core::marker::PhantomPinned;
+use crate::{
+ fmt,
+ prelude::*,
+ str::CStr,
+ uaccess::UserSliceReader, //
+};
+
#[cfg(CONFIG_DEBUG_FS)]
use core::mem::ManuallyDrop;
-use core::ops::Deref;
+use core::{
+ marker::{
+ PhantomData,
+ PhantomPinned, //
+ },
+ ops::Deref,
+};
mod traits;
-pub use traits::{BinaryReader, BinaryReaderMut, BinaryWriter, Reader, Writer};
+pub use traits::{
+ BinaryReader,
+ BinaryReaderMut,
+ BinaryWriter,
+ Reader,
+ Writer, //
+};
mod callback_adapters;
-use callback_adapters::{FormatAdapter, NoWriter, WritableAdapter};
+use callback_adapters::{
+ FormatAdapter,
+ NoWriter,
+ WritableAdapter, //
+};
+
mod file_ops;
use file_ops::{
- BinaryReadFile, BinaryReadWriteFile, BinaryWriteFile, FileOps, ReadFile, ReadWriteFile,
- WriteFile,
+ BinaryReadFile,
+ BinaryReadWriteFile,
+ BinaryWriteFile,
+ FileOps,
+ ReadFile,
+ ReadWriteFile,
+ WriteFile, //
};
+
#[cfg(CONFIG_DEBUG_FS)]
mod entry;
#[cfg(CONFIG_DEBUG_FS)]
@@ -102,9 +126,8 @@ impl Dir {
/// # Examples
///
/// ```
- /// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
- /// let debugfs = Dir::new(c_str!("parent"));
+ /// let debugfs = Dir::new(c"parent");
/// ```
pub fn new(name: &CStr) -> Self {
Dir::create(name, None)
@@ -115,10 +138,9 @@ impl Dir {
/// # Examples
///
/// ```
- /// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
- /// let parent = Dir::new(c_str!("parent"));
- /// let child = parent.subdir(c_str!("child"));
+ /// let parent = Dir::new(c"parent");
+ /// let child = parent.subdir(c"child");
/// ```
pub fn subdir(&self, name: &CStr) -> Self {
Dir::create(name, Some(self))
@@ -132,11 +154,10 @@ impl Dir {
/// # Examples
///
/// ```
- /// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// # use kernel::prelude::*;
- /// # let dir = Dir::new(c_str!("my_debugfs_dir"));
- /// let file = KBox::pin_init(dir.read_only_file(c_str!("foo"), 200), GFP_KERNEL)?;
+ /// # let dir = Dir::new(c"my_debugfs_dir");
+ /// let file = KBox::pin_init(dir.read_only_file(c"foo", 200), GFP_KERNEL)?;
/// // "my_debugfs_dir/foo" now contains the number 200.
/// // The file is removed when `file` is dropped.
/// # Ok::<(), Error>(())
@@ -161,11 +182,10 @@ impl Dir {
/// # Examples
///
/// ```
- /// # use kernel::c_str;
/// # use kernel::debugfs::Dir;
/// # use kernel::prelude::*;
- /// # let dir = Dir::new(c_str!("my_debugfs_dir"));
- /// let file = KBox::pin_init(dir.read_binary_file(c_str!("foo"), [0x1, 0x2]), GFP_KERNEL)?;
+ /// # let dir = Dir::new(c"my_debugfs_dir");
+ /// let file = KBox::pin_init(dir.read_binary_file(c"foo", [0x1, 0x2]), GFP_KERNEL)?;
/// # Ok::<(), Error>(())
/// ```
pub fn read_binary_file<'a, T, E: 'a>(
@@ -187,21 +207,25 @@ impl Dir {
/// # Examples
///
/// ```
- /// # use core::sync::atomic::{AtomicU32, Ordering};
- /// # use kernel::c_str;
- /// # use kernel::debugfs::Dir;
- /// # use kernel::prelude::*;
- /// # let dir = Dir::new(c_str!("foo"));
+ /// # use kernel::{
+ /// # debugfs::Dir,
+ /// # prelude::*,
+ /// # sync::atomic::{
+ /// # Atomic,
+ /// # Relaxed,
+ /// # },
+ /// # };
+ /// # let dir = Dir::new(c"foo");
/// let file = KBox::pin_init(
- /// dir.read_callback_file(c_str!("bar"),
- /// AtomicU32::new(3),
+ /// dir.read_callback_file(c"bar",
+ /// Atomic::<u32>::new(3),
/// &|val, f| {
- /// let out = val.load(Ordering::Relaxed);
+ /// let out = val.load(Relaxed);
/// writeln!(f, "{out:#010x}")
/// }),
/// GFP_KERNEL)?;
/// // Reading "foo/bar" will show "0x00000003".
- /// file.store(10, Ordering::Relaxed);
+ /// file.store(10, Relaxed);
/// // Reading "foo/bar" will now show "0x0000000a".
/// # Ok::<(), Error>(())
/// ```
diff --git a/rust/kernel/debugfs/callback_adapters.rs b/rust/kernel/debugfs/callback_adapters.rs
index a260d8dee051..dee7d021e18c 100644
--- a/rust/kernel/debugfs/callback_adapters.rs
+++ b/rust/kernel/debugfs/callback_adapters.rs
@@ -4,12 +4,21 @@
//! Adapters which allow the user to supply a write or read implementation as a value rather
//! than a trait implementation. If provided, it will override the trait implementation.
-use super::{Reader, Writer};
-use crate::fmt;
-use crate::prelude::*;
-use crate::uaccess::UserSliceReader;
-use core::marker::PhantomData;
-use core::ops::Deref;
+use super::{
+ Reader,
+ Writer, //
+};
+
+use crate::{
+ fmt,
+ prelude::*,
+ uaccess::UserSliceReader, //
+};
+
+use core::{
+ marker::PhantomData,
+ ops::Deref, //
+};
/// # Safety
///
diff --git a/rust/kernel/debugfs/entry.rs b/rust/kernel/debugfs/entry.rs
index a30bf8f29679..46aad64896ec 100644
--- a/rust/kernel/debugfs/entry.rs
+++ b/rust/kernel/debugfs/entry.rs
@@ -1,10 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2025 Google LLC.
-use crate::debugfs::file_ops::FileOps;
-use crate::ffi::c_void;
-use crate::str::{CStr, CStrExt as _};
-use crate::sync::Arc;
+use crate::{
+ debugfs::file_ops::FileOps,
+ prelude::*,
+ str::{
+ CStr,
+ CStrExt as _, //
+ },
+ sync::Arc,
+};
+
use core::marker::PhantomData;
/// Owning handle to a DebugFS entry.
diff --git a/rust/kernel/debugfs/file_ops.rs b/rust/kernel/debugfs/file_ops.rs
index 8a0442d6dd7a..f15908f71c4a 100644
--- a/rust/kernel/debugfs/file_ops.rs
+++ b/rust/kernel/debugfs/file_ops.rs
@@ -1,14 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2025 Google LLC.
-use super::{BinaryReader, BinaryWriter, Reader, Writer};
-use crate::debugfs::callback_adapters::Adapter;
-use crate::fmt;
-use crate::fs::file;
-use crate::prelude::*;
-use crate::seq_file::SeqFile;
-use crate::seq_print;
-use crate::uaccess::UserSlice;
+use super::{
+ BinaryReader,
+ BinaryWriter,
+ Reader,
+ Writer, //
+};
+
+use crate::{
+ debugfs::callback_adapters::Adapter,
+ fmt,
+ fs::file,
+ prelude::*,
+ seq_file::SeqFile,
+ seq_print,
+ uaccess::UserSlice, //
+};
+
use core::marker::PhantomData;
#[cfg(CONFIG_DEBUG_FS)]
@@ -126,8 +135,7 @@ impl<T: Writer + Sync> ReadFile<T> for T {
llseek: Some(bindings::seq_lseek),
release: Some(bindings::single_release),
open: Some(writer_open::<Self>),
- // SAFETY: `file_operations` supports zeroes in all fields.
- ..unsafe { core::mem::zeroed() }
+ ..pin_init::zeroed()
};
// SAFETY: `operations` is all stock `seq_file` implementations except for `writer_open`.
// `open`'s only requirement beyond what is provided to all open functions is that the
@@ -179,8 +187,7 @@ impl<T: Writer + Reader + Sync> ReadWriteFile<T> for T {
write: Some(write::<T>),
llseek: Some(bindings::seq_lseek),
release: Some(bindings::single_release),
- // SAFETY: `file_operations` supports zeroes in all fields.
- ..unsafe { core::mem::zeroed() }
+ ..pin_init::zeroed()
};
// SAFETY: `operations` is all stock `seq_file` implementations except for `writer_open`
// and `write`.
@@ -235,8 +242,7 @@ impl<T: Reader + Sync> WriteFile<T> for T {
open: Some(write_only_open),
write: Some(write_only_write::<T>),
llseek: Some(bindings::noop_llseek),
- // SAFETY: `file_operations` supports zeroes in all fields.
- ..unsafe { core::mem::zeroed() }
+ ..pin_init::zeroed()
};
// SAFETY:
// * `write_only_open` populates the file private data with the inode private data
@@ -288,8 +294,7 @@ impl<T: BinaryWriter + Sync> BinaryReadFile<T> for T {
read: Some(blob_read::<T>),
llseek: Some(bindings::default_llseek),
open: Some(bindings::simple_open),
- // SAFETY: `file_operations` supports zeroes in all fields.
- ..unsafe { core::mem::zeroed() }
+ ..pin_init::zeroed()
};
// SAFETY:
@@ -343,8 +348,7 @@ impl<T: BinaryReader + Sync> BinaryWriteFile<T> for T {
write: Some(blob_write::<T>),
llseek: Some(bindings::default_llseek),
open: Some(bindings::simple_open),
- // SAFETY: `file_operations` supports zeroes in all fields.
- ..unsafe { core::mem::zeroed() }
+ ..pin_init::zeroed()
};
// SAFETY:
@@ -369,8 +373,7 @@ impl<T: BinaryWriter + BinaryReader + Sync> BinaryReadWriteFile<T> for T {
write: Some(blob_write::<T>),
llseek: Some(bindings::default_llseek),
open: Some(bindings::simple_open),
- // SAFETY: `file_operations` supports zeroes in all fields.
- ..unsafe { core::mem::zeroed() }
+ ..pin_init::zeroed()
};
// SAFETY:
diff --git a/rust/kernel/debugfs/traits.rs b/rust/kernel/debugfs/traits.rs
index 3eee60463fd5..8c39524b6a99 100644
--- a/rust/kernel/debugfs/traits.rs
+++ b/rust/kernel/debugfs/traits.rs
@@ -3,17 +3,38 @@
//! Traits for rendering or updating values exported to DebugFS.
-use crate::alloc::Allocator;
-use crate::fmt;
-use crate::fs::file;
-use crate::prelude::*;
-use crate::sync::atomic::{Atomic, AtomicBasicOps, AtomicType, Relaxed};
-use crate::sync::Arc;
-use crate::sync::Mutex;
-use crate::transmute::{AsBytes, FromBytes};
-use crate::uaccess::{UserSliceReader, UserSliceWriter};
-use core::ops::{Deref, DerefMut};
-use core::str::FromStr;
+use crate::{
+ alloc::Allocator,
+ fmt,
+ fs::file,
+ prelude::*,
+ sync::{
+ atomic::{
+ Atomic,
+ AtomicBasicOps,
+ AtomicType,
+ Relaxed, //
+ },
+ Arc,
+ Mutex, //
+ },
+ transmute::{
+ AsBytes,
+ FromBytes, //
+ },
+ uaccess::{
+ UserSliceReader,
+ UserSliceWriter, //
+ },
+};
+
+use core::{
+ ops::{
+ Deref,
+ DerefMut, //
+ },
+ str::FromStr,
+};
/// A trait for types that can be written into a string.
///
diff --git a/rust/kernel/device.rs b/rust/kernel/device.rs
index 031720bf5d8c..94e0548e7687 100644
--- a/rust/kernel/device.rs
+++ b/rust/kernel/device.rs
@@ -5,15 +5,20 @@
//! C header: [`include/linux/device.h`](srctree/include/linux/device.h)
use crate::{
- bindings, fmt,
+ bindings,
+ fmt,
prelude::*,
sync::aref::ARef,
- types::{ForeignOwnable, Opaque},
+ types::{
+ ForeignOwnable,
+ Opaque, //
+ }, //
+};
+use core::{
+ any::TypeId,
+ marker::PhantomData,
+ ptr, //
};
-use core::{any::TypeId, marker::PhantomData, ptr};
-
-#[cfg(CONFIG_PRINTK)]
-use crate::c_str;
pub mod property;
@@ -158,7 +163,7 @@ static_assert!(core::mem::size_of::<bindings::driver_type>() >= core::mem::size_
/// `bindings::device::release` is valid to be called from any thread, hence `ARef<Device>` can be
/// dropped from any thread.
///
-/// [`AlwaysRefCounted`]: kernel::types::AlwaysRefCounted
+/// [`AlwaysRefCounted`]: kernel::sync::aref::AlwaysRefCounted
/// [`impl_device_context_deref`]: kernel::impl_device_context_deref
/// [`platform::Device`]: kernel::platform::Device
#[repr(transparent)]
@@ -464,7 +469,7 @@ impl<Ctx: DeviceContext> Device<Ctx> {
bindings::_dev_printk(
klevel.as_ptr().cast::<crate::ffi::c_char>(),
self.as_raw(),
- c_str!("%pA").as_char_ptr(),
+ c"%pA".as_char_ptr(),
core::ptr::from_ref(&msg).cast::<crate::ffi::c_void>(),
)
};
@@ -541,7 +546,7 @@ pub trait DeviceContext: private::Sealed {}
/// [`Device<Normal>`]. It is the only [`DeviceContext`] for which it is valid to implement
/// [`AlwaysRefCounted`] for.
///
-/// [`AlwaysRefCounted`]: kernel::types::AlwaysRefCounted
+/// [`AlwaysRefCounted`]: kernel::sync::aref::AlwaysRefCounted
pub struct Normal;
/// The [`Core`] context is the context of a bus specific device when it appears as argument of
@@ -596,6 +601,13 @@ impl DeviceContext for Core {}
impl DeviceContext for CoreInternal {}
impl DeviceContext for Normal {}
+impl<Ctx: DeviceContext> AsRef<Device<Ctx>> for Device<Ctx> {
+ #[inline]
+ fn as_ref(&self) -> &Device<Ctx> {
+ self
+ }
+}
+
/// Convert device references to bus device references.
///
/// Bus devices can implement this trait to allow abstractions to provide the bus device in
@@ -715,7 +727,7 @@ macro_rules! impl_device_context_into_aref {
macro_rules! dev_printk {
($method:ident, $dev:expr, $($f:tt)*) => {
{
- ($dev).$method($crate::prelude::fmt!($($f)*));
+ $crate::device::Device::$method($dev.as_ref(), $crate::prelude::fmt!($($f)*))
}
}
}
diff --git a/rust/kernel/device/property.rs b/rust/kernel/device/property.rs
index 3a332a8c53a9..5aead835fbbc 100644
--- a/rust/kernel/device/property.rs
+++ b/rust/kernel/device/property.rs
@@ -14,7 +14,8 @@ use crate::{
fmt,
prelude::*,
str::{CStr, CString},
- types::{ARef, Opaque},
+ sync::aref::ARef,
+ types::Opaque,
};
/// A reference-counted fwnode_handle.
@@ -178,11 +179,11 @@ impl FwNode {
/// # Examples
///
/// ```
- /// # use kernel::{c_str, device::{Device, property::FwNode}, str::CString};
+ /// # use kernel::{device::{Device, property::FwNode}, str::CString};
/// fn examples(dev: &Device) -> Result {
/// let fwnode = dev.fwnode().ok_or(ENOENT)?;
- /// let b: u32 = fwnode.property_read(c_str!("some-number")).required_by(dev)?;
- /// if let Some(s) = fwnode.property_read::<CString>(c_str!("some-str")).optional() {
+ /// let b: u32 = fwnode.property_read(c"some-number").required_by(dev)?;
+ /// if let Some(s) = fwnode.property_read::<CString>(c"some-str").optional() {
/// // ...
/// }
/// Ok(())
@@ -359,7 +360,7 @@ impl fmt::Debug for FwNodeReferenceArgs {
}
// SAFETY: Instances of `FwNode` are always reference-counted.
-unsafe impl crate::types::AlwaysRefCounted for FwNode {
+unsafe impl crate::sync::aref::AlwaysRefCounted for FwNode {
fn inc_ref(&self) {
// SAFETY: The existence of a shared reference guarantees that the
// refcount is non-zero.
diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs
index 835d9c11948e..6afe196be42c 100644
--- a/rust/kernel/devres.rs
+++ b/rust/kernel/devres.rs
@@ -8,30 +8,24 @@
use crate::{
alloc::Flags,
bindings,
- device::{Bound, Device},
- error::{to_result, Error, Result},
- ffi::c_void,
+ device::{
+ Bound,
+ Device, //
+ },
+ error::to_result,
prelude::*,
- revocable::{Revocable, RevocableGuard},
- sync::{aref::ARef, rcu, Completion},
- types::{ForeignOwnable, Opaque, ScopeGuard},
+ revocable::{
+ Revocable,
+ RevocableGuard, //
+ },
+ sync::{
+ aref::ARef,
+ rcu,
+ Arc, //
+ },
+ types::ForeignOwnable,
};
-use pin_init::Wrapper;
-
-/// [`Devres`] inner data accessed from [`Devres::callback`].
-#[pin_data]
-struct Inner<T: Send> {
- #[pin]
- data: Revocable<T>,
- /// Tracks whether [`Devres::callback`] has been completed.
- #[pin]
- devm: Completion,
- /// Tracks whether revoking [`Self::data`] has been completed.
- #[pin]
- revoke: Completion,
-}
-
/// This abstraction is meant to be used by subsystems to containerize [`Device`] bound resources to
/// manage their lifetime.
///
@@ -61,14 +55,17 @@ struct Inner<T: Send> {
/// devres::Devres,
/// io::{
/// Io,
-/// IoRaw,
-/// PhysAddr,
+/// IoKnownSize,
+/// Mmio,
+/// MmioRaw,
+/// PhysAddr, //
/// },
+/// prelude::*,
/// };
/// use core::ops::Deref;
///
/// // See also [`pci::Bar`] for a real example.
-/// struct IoMem<const SIZE: usize>(IoRaw<SIZE>);
+/// struct IoMem<const SIZE: usize>(MmioRaw<SIZE>);
///
/// impl<const SIZE: usize> IoMem<SIZE> {
/// /// # Safety
@@ -83,7 +80,7 @@ struct Inner<T: Send> {
/// return Err(ENOMEM);
/// }
///
-/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?))
+/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))
/// }
/// }
///
@@ -95,28 +92,23 @@ struct Inner<T: Send> {
/// }
///
/// impl<const SIZE: usize> Deref for IoMem<SIZE> {
-/// type Target = Io<SIZE>;
+/// type Target = Mmio<SIZE>;
///
/// fn deref(&self) -> &Self::Target {
/// // SAFETY: The memory range stored in `self` has been properly mapped in `Self::new`.
-/// unsafe { Io::from_raw(&self.0) }
+/// unsafe { Mmio::from_raw(&self.0) }
/// }
/// }
/// # fn no_run(dev: &Device<Bound>) -> Result<(), Error> {
/// // SAFETY: Invalid usage for example purposes.
/// let iomem = unsafe { IoMem::<{ core::mem::size_of::<u32>() }>::new(0xBAAAAAAD)? };
-/// let devres = KBox::pin_init(Devres::new(dev, iomem), GFP_KERNEL)?;
+/// let devres = Devres::new(dev, iomem)?;
///
/// let res = devres.try_access().ok_or(ENXIO)?;
/// res.write8(0x42, 0x0);
/// # Ok(())
/// # }
/// ```
-///
-/// # Invariants
-///
-/// `Self::inner` is guaranteed to be initialized and is always accessed read-only.
-#[pin_data(PinnedDrop)]
pub struct Devres<T: Send> {
dev: ARef<Device>,
/// Pointer to [`Self::devres_callback`].
@@ -124,14 +116,7 @@ pub struct Devres<T: Send> {
/// Has to be stored, since Rust does not guarantee to always return the same address for a
/// function. However, the C API uses the address as a key.
callback: unsafe extern "C" fn(*mut c_void),
- /// Contains all the fields shared with [`Self::callback`].
- // TODO: Replace with `UnsafePinned`, once available.
- //
- // Subsequently, the `drop_in_place()` in `Devres::drop` and `Devres::new` as well as the
- // explicit `Send` and `Sync' impls can be removed.
- #[pin]
- inner: Opaque<Inner<T>>,
- _add_action: (),
+ data: Arc<Revocable<T>>,
}
impl<T: Send> Devres<T> {
@@ -139,74 +124,48 @@ impl<T: Send> Devres<T> {
///
/// The `data` encapsulated within the returned `Devres` instance' `data` will be
/// (revoked)[`Revocable`] once the device is detached.
- pub fn new<'a, E>(
- dev: &'a Device<Bound>,
- data: impl PinInit<T, E> + 'a,
- ) -> impl PinInit<Self, Error> + 'a
+ pub fn new<E>(dev: &Device<Bound>, data: impl PinInit<T, E>) -> Result<Self>
where
- T: 'a,
Error: From<E>,
{
- try_pin_init!(&this in Self {
- dev: dev.into(),
- callback: Self::devres_callback,
- // INVARIANT: `inner` is properly initialized.
- inner <- Opaque::pin_init(try_pin_init!(Inner {
- devm <- Completion::new(),
- revoke <- Completion::new(),
- data <- Revocable::new(data),
- })),
- // TODO: Replace with "initializer code blocks" [1] once available.
- //
- // [1] https://github.com/Rust-for-Linux/pin-init/pull/69
- _add_action: {
- // SAFETY: `this` is a valid pointer to uninitialized memory.
- let inner = unsafe { &raw mut (*this.as_ptr()).inner };
+ let callback = Self::devres_callback;
+ let data = Arc::pin_init(Revocable::new(data), GFP_KERNEL)?;
+ let devres_data = data.clone();
- // SAFETY:
- // - `dev.as_raw()` is a pointer to a valid bound device.
- // - `inner` is guaranteed to be a valid for the duration of the lifetime of `Self`.
- // - `devm_add_action()` is guaranteed not to call `callback` until `this` has been
- // properly initialized, because we require `dev` (i.e. the *bound* device) to
- // live at least as long as the returned `impl PinInit<Self, Error>`.
- to_result(unsafe {
- bindings::devm_add_action(dev.as_raw(), Some(*callback), inner.cast())
- }).inspect_err(|_| {
- let inner = Opaque::cast_into(inner);
+ // SAFETY:
+ // - `dev.as_raw()` is a pointer to a valid bound device.
+ // - `data` is guaranteed to be a valid for the duration of the lifetime of `Self`.
+ // - `devm_add_action()` is guaranteed not to call `callback` for the entire lifetime of
+ // `dev`.
+ to_result(unsafe {
+ bindings::devm_add_action(
+ dev.as_raw(),
+ Some(callback),
+ Arc::as_ptr(&data).cast_mut().cast(),
+ )
+ })?;
- // SAFETY: `inner` is a valid pointer to an `Inner<T>` and valid for both reads
- // and writes.
- unsafe { core::ptr::drop_in_place(inner) };
- })?;
- },
- })
- }
+ // `devm_add_action()` was successful and has consumed the reference count.
+ core::mem::forget(devres_data);
- fn inner(&self) -> &Inner<T> {
- // SAFETY: By the type invairants of `Self`, `inner` is properly initialized and always
- // accessed read-only.
- unsafe { &*self.inner.get() }
+ Ok(Self {
+ dev: dev.into(),
+ callback,
+ data,
+ })
}
fn data(&self) -> &Revocable<T> {
- &self.inner().data
+ &self.data
}
#[allow(clippy::missing_safety_doc)]
unsafe extern "C" fn devres_callback(ptr: *mut kernel::ffi::c_void) {
- // SAFETY: In `Self::new` we've passed a valid pointer to `Inner` to `devm_add_action()`,
- // hence `ptr` must be a valid pointer to `Inner`.
- let inner = unsafe { &*ptr.cast::<Inner<T>>() };
-
- // Ensure that `inner` can't be used anymore after we signal completion of this callback.
- let inner = ScopeGuard::new_with_data(inner, |inner| inner.devm.complete_all());
+ // SAFETY: In `Self::new` we've passed a valid pointer of `Revocable<T>` to
+ // `devm_add_action()`, hence `ptr` must be a valid pointer to `Revocable<T>`.
+ let data = unsafe { Arc::from_raw(ptr.cast::<Revocable<T>>()) };
- if !inner.data.revoke() {
- // If `revoke()` returns false, it means that `Devres::drop` already started revoking
- // `data` for us. Hence we have to wait until `Devres::drop` signals that it
- // completed revoking `data`.
- inner.revoke.wait_for_completion();
- }
+ data.revoke();
}
fn remove_action(&self) -> bool {
@@ -218,7 +177,7 @@ impl<T: Send> Devres<T> {
bindings::devm_remove_action_nowarn(
self.dev.as_raw(),
Some(self.callback),
- core::ptr::from_ref(self.inner()).cast_mut().cast(),
+ core::ptr::from_ref(self.data()).cast_mut().cast(),
)
} == 0)
}
@@ -241,8 +200,16 @@ impl<T: Send> Devres<T> {
/// # Examples
///
/// ```no_run
- /// # #![cfg(CONFIG_PCI)]
- /// # use kernel::{device::Core, devres::Devres, pci};
+ /// #![cfg(CONFIG_PCI)]
+ /// use kernel::{
+ /// device::Core,
+ /// devres::Devres,
+ /// io::{
+ /// Io,
+ /// IoKnownSize, //
+ /// },
+ /// pci, //
+ /// };
///
/// fn from_core(dev: &pci::Device<Core>, devres: Devres<pci::Bar<0x4>>) -> Result {
/// let bar = devres.access(dev.as_ref())?;
@@ -289,31 +256,19 @@ unsafe impl<T: Send> Send for Devres<T> {}
// SAFETY: `Devres` can be shared with any task, if `T: Sync`.
unsafe impl<T: Send + Sync> Sync for Devres<T> {}
-#[pinned_drop]
-impl<T: Send> PinnedDrop for Devres<T> {
- fn drop(self: Pin<&mut Self>) {
+impl<T: Send> Drop for Devres<T> {
+ fn drop(&mut self) {
// SAFETY: When `drop` runs, it is guaranteed that nobody is accessing the revocable data
// anymore, hence it is safe not to wait for the grace period to finish.
if unsafe { self.data().revoke_nosync() } {
// We revoked `self.data` before the devres action did, hence try to remove it.
- if !self.remove_action() {
- // We could not remove the devres action, which means that it now runs concurrently,
- // hence signal that `self.data` has been revoked by us successfully.
- self.inner().revoke.complete_all();
-
- // Wait for `Self::devres_callback` to be done using this object.
- self.inner().devm.wait_for_completion();
+ if self.remove_action() {
+ // SAFETY: In `Self::new` we have taken an additional reference count of `self.data`
+ // for `devm_add_action()`. Since `remove_action()` was successful, we have to drop
+ // this additional reference count.
+ drop(unsafe { Arc::from_raw(Arc::as_ptr(&self.data)) });
}
- } else {
- // `Self::devres_callback` revokes `self.data` for us, hence wait for it to be done
- // using this object.
- self.inner().devm.wait_for_completion();
}
-
- // INVARIANT: At this point it is guaranteed that `inner` can't be accessed any more.
- //
- // SAFETY: `inner` is valid for dropping.
- unsafe { core::ptr::drop_in_place(self.inner.get()) };
}
}
@@ -345,7 +300,13 @@ where
/// # Examples
///
/// ```no_run
-/// use kernel::{device::{Bound, Device}, devres};
+/// use kernel::{
+/// device::{
+/// Bound,
+/// Device, //
+/// },
+/// devres, //
+/// };
///
/// /// Registration of e.g. a class device, IRQ, etc.
/// struct Registration;
diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs
index acc65b1e0f24..909d56fd5118 100644
--- a/rust/kernel/dma.rs
+++ b/rust/kernel/dma.rs
@@ -85,6 +85,23 @@ pub trait Device: AsRef<device::Device<Core>> {
bindings::dma_set_mask_and_coherent(self.as_ref().as_raw(), mask.value())
})
}
+
+ /// Set the maximum size of a single DMA segment the device may request.
+ ///
+ /// This method is usually called once from `probe()` as soon as the device capabilities are
+ /// known.
+ ///
+ /// # Safety
+ ///
+ /// This method must not be called concurrently with any DMA allocation or mapping primitives,
+ /// such as [`CoherentAllocation::alloc_attrs`].
+ unsafe fn dma_set_max_seg_size(&self, size: u32) {
+ // SAFETY:
+ // - By the type invariant of `device::Device`, `self.as_ref().as_raw()` is valid.
+ // - The safety requirement of this function guarantees that there are no concurrent calls
+ // to DMA allocation and mapping primitives using this parameter.
+ unsafe { bindings::dma_set_max_seg_size(self.as_ref().as_raw(), size) }
+ }
}
/// A DMA mask that holds a bitmask with the lowest `n` bits set.
diff --git a/rust/kernel/driver.rs b/rust/kernel/driver.rs
index bee3ae21a27b..36de8098754d 100644
--- a/rust/kernel/driver.rs
+++ b/rust/kernel/driver.rs
@@ -94,10 +94,14 @@
//! [`device_id`]: kernel::device_id
//! [`module_driver`]: kernel::module_driver
-use crate::error::{Error, Result};
-use crate::{acpi, device, of, str::CStr, try_pin_init, types::Opaque, ThisModule};
-use core::pin::Pin;
-use pin_init::{pin_data, pinned_drop, PinInit};
+use crate::{
+ acpi,
+ device,
+ of,
+ prelude::*,
+ types::Opaque,
+ ThisModule, //
+};
/// Trait describing the layout of a specific device driver.
///
diff --git a/rust/kernel/faux.rs b/rust/kernel/faux.rs
index 7fe2dd197e37..43b4974f48cd 100644
--- a/rust/kernel/faux.rs
+++ b/rust/kernel/faux.rs
@@ -6,8 +6,17 @@
//!
//! C header: [`include/linux/device/faux.h`](srctree/include/linux/device/faux.h)
-use crate::{bindings, device, error::code::*, prelude::*};
-use core::ptr::{addr_of_mut, null, null_mut, NonNull};
+use crate::{
+ bindings,
+ device,
+ prelude::*, //
+};
+use core::ptr::{
+ addr_of_mut,
+ null,
+ null_mut,
+ NonNull, //
+};
/// The registration of a faux device.
///
diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs
index b64b11f75a35..c1cca7b438c3 100644
--- a/rust/kernel/io.rs
+++ b/rust/kernel/io.rs
@@ -32,16 +32,16 @@ pub type ResourceSize = bindings::resource_size_t;
/// By itself, the existence of an instance of this structure does not provide any guarantees that
/// the represented MMIO region does exist or is properly mapped.
///
-/// Instead, the bus specific MMIO implementation must convert this raw representation into an `Io`
-/// instance providing the actual memory accessors. Only by the conversion into an `Io` structure
-/// any guarantees are given.
-pub struct IoRaw<const SIZE: usize = 0> {
+/// Instead, the bus specific MMIO implementation must convert this raw representation into an
+/// `Mmio` instance providing the actual memory accessors. Only by the conversion into an `Mmio`
+/// structure any guarantees are given.
+pub struct MmioRaw<const SIZE: usize = 0> {
addr: usize,
maxsize: usize,
}
-impl<const SIZE: usize> IoRaw<SIZE> {
- /// Returns a new `IoRaw` instance on success, an error otherwise.
+impl<const SIZE: usize> MmioRaw<SIZE> {
+ /// Returns a new `MmioRaw` instance on success, an error otherwise.
pub fn new(addr: usize, maxsize: usize) -> Result<Self> {
if maxsize < SIZE {
return Err(EINVAL);
@@ -81,14 +81,16 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// ffi::c_void,
/// io::{
/// Io,
-/// IoRaw,
+/// IoKnownSize,
+/// Mmio,
+/// MmioRaw,
/// PhysAddr,
/// },
/// };
/// use core::ops::Deref;
///
-/// // See also [`pci::Bar`] for a real example.
-/// struct IoMem<const SIZE: usize>(IoRaw<SIZE>);
+/// // See also `pci::Bar` for a real example.
+/// struct IoMem<const SIZE: usize>(MmioRaw<SIZE>);
///
/// impl<const SIZE: usize> IoMem<SIZE> {
/// /// # Safety
@@ -103,7 +105,7 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// return Err(ENOMEM);
/// }
///
-/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?))
+/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))
/// }
/// }
///
@@ -115,11 +117,11 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// }
///
/// impl<const SIZE: usize> Deref for IoMem<SIZE> {
-/// type Target = Io<SIZE>;
+/// type Target = Mmio<SIZE>;
///
/// fn deref(&self) -> &Self::Target {
/// // SAFETY: The memory range stored in `self` has been properly mapped in `Self::new`.
-/// unsafe { Io::from_raw(&self.0) }
+/// unsafe { Mmio::from_raw(&self.0) }
/// }
/// }
///
@@ -133,10 +135,67 @@ impl<const SIZE: usize> IoRaw<SIZE> {
/// # }
/// ```
#[repr(transparent)]
-pub struct Io<const SIZE: usize = 0>(IoRaw<SIZE>);
+pub struct Mmio<const SIZE: usize = 0>(MmioRaw<SIZE>);
+
+/// Internal helper macros used to invoke C MMIO read functions.
+///
+/// This macro is intended to be used by higher-level MMIO access macros (define_read) and provides
+/// a unified expansion for infallible vs. fallible read semantics. It emits a direct call into the
+/// corresponding C helper and performs the required cast to the Rust return type.
+///
+/// # Parameters
+///
+/// * `$c_fn` – The C function performing the MMIO read.
+/// * `$self` – The I/O backend object.
+/// * `$ty` – The type of the value to be read.
+/// * `$addr` – The MMIO address to read.
+///
+/// This macro does not perform any validation; all invariants must be upheld by the higher-level
+/// abstraction invoking it.
+macro_rules! call_mmio_read {
+ (infallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) => {
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ unsafe { bindings::$c_fn($addr as *const c_void) as $type }
+ };
+
+ (fallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) => {{
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ Ok(unsafe { bindings::$c_fn($addr as *const c_void) as $type })
+ }};
+}
+
+/// Internal helper macros used to invoke C MMIO write functions.
+///
+/// This macro is intended to be used by higher-level MMIO access macros (define_write) and provides
+/// a unified expansion for infallible vs. fallible write semantics. It emits a direct call into the
+/// corresponding C helper and performs the required cast to the Rust return type.
+///
+/// # Parameters
+///
+/// * `$c_fn` – The C function performing the MMIO write.
+/// * `$self` – The I/O backend object.
+/// * `$ty` – The type of the written value.
+/// * `$addr` – The MMIO address to write.
+/// * `$value` – The value to write.
+///
+/// This macro does not perform any validation; all invariants must be upheld by the higher-level
+/// abstraction invoking it.
+macro_rules! call_mmio_write {
+ (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ unsafe { bindings::$c_fn($value, $addr as *mut c_void) }
+ };
+
+ (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {{
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ unsafe { bindings::$c_fn($value, $addr as *mut c_void) };
+ Ok(())
+ }};
+}
macro_rules! define_read {
- ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_name:ty) => {
+ (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident($c_fn:ident) ->
+ $type_name:ty) => {
/// Read IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
@@ -144,29 +203,34 @@ macro_rules! define_read {
$(#[$attr])*
// Always inline to optimize out error path of `io_addr_assert`.
#[inline(always)]
- pub fn $name(&self, offset: usize) -> $type_name {
+ $vis fn $name(&self, offset: usize) -> $type_name {
let addr = self.io_addr_assert::<$type_name>(offset);
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- unsafe { bindings::$c_fn(addr as *const c_void) }
+ // SAFETY: By the type invariant `addr` is a valid address for IO operations.
+ $call_macro!(infallible, $c_fn, self, $type_name, addr)
}
+ };
+ (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ident($c_fn:ident) ->
+ $type_name:ty) => {
/// Read IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
/// out of bounds.
$(#[$attr])*
- pub fn $try_name(&self, offset: usize) -> Result<$type_name> {
+ $vis fn $try_name(&self, offset: usize) -> Result<$type_name> {
let addr = self.io_addr::<$type_name>(offset)?;
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- Ok(unsafe { bindings::$c_fn(addr as *const c_void) })
+ // SAFETY: By the type invariant `addr` is a valid address for IO operations.
+ $call_macro!(fallible, $c_fn, self, $type_name, addr)
}
};
}
+pub(crate) use define_read;
macro_rules! define_write {
- ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_name:ty) => {
+ (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident($c_fn:ident) <-
+ $type_name:ty) => {
/// Write IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
@@ -174,65 +238,80 @@ macro_rules! define_write {
$(#[$attr])*
// Always inline to optimize out error path of `io_addr_assert`.
#[inline(always)]
- pub fn $name(&self, value: $type_name, offset: usize) {
+ $vis fn $name(&self, value: $type_name, offset: usize) {
let addr = self.io_addr_assert::<$type_name>(offset);
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- unsafe { bindings::$c_fn(value, addr as *mut c_void) }
+ $call_macro!(infallible, $c_fn, self, $type_name, addr, value);
}
+ };
+ (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ident($c_fn:ident) <-
+ $type_name:ty) => {
/// Write IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
/// out of bounds.
$(#[$attr])*
- pub fn $try_name(&self, value: $type_name, offset: usize) -> Result {
+ $vis fn $try_name(&self, value: $type_name, offset: usize) -> Result {
let addr = self.io_addr::<$type_name>(offset)?;
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- unsafe { bindings::$c_fn(value, addr as *mut c_void) }
- Ok(())
+ $call_macro!(fallible, $c_fn, self, $type_name, addr, value)
}
};
}
-
-impl<const SIZE: usize> Io<SIZE> {
- /// Converts an `IoRaw` into an `Io` instance, providing the accessors to the MMIO mapping.
- ///
- /// # Safety
- ///
- /// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size
- /// `maxsize`.
- pub unsafe fn from_raw(raw: &IoRaw<SIZE>) -> &Self {
- // SAFETY: `Io` is a transparent wrapper around `IoRaw`.
- unsafe { &*core::ptr::from_ref(raw).cast() }
+pub(crate) use define_write;
+
+/// Checks whether an access of type `U` at the given `offset`
+/// is valid within this region.
+#[inline]
+const fn offset_valid<U>(offset: usize, size: usize) -> bool {
+ let type_size = core::mem::size_of::<U>();
+ if let Some(end) = offset.checked_add(type_size) {
+ end <= size && offset % type_size == 0
+ } else {
+ false
}
+}
+
+/// Marker trait indicating that an I/O backend supports operations of a certain type.
+///
+/// Different I/O backends can implement this trait to expose only the operations they support.
+///
+/// For example, a PCI configuration space may implement `IoCapable<u8>`, `IoCapable<u16>`,
+/// and `IoCapable<u32>`, but not `IoCapable<u64>`, while an MMIO region on a 64-bit
+/// system might implement all four.
+pub trait IoCapable<T> {}
+/// Types implementing this trait (e.g. MMIO BARs or PCI config regions)
+/// can perform I/O operations on regions of memory.
+///
+/// This is an abstract representation to be implemented by arbitrary I/O
+/// backends (e.g. MMIO, PCI config space, etc.).
+///
+/// The [`Io`] trait provides:
+/// - Base address and size information
+/// - Helper methods for offset validation and address calculation
+/// - Fallible (runtime checked) accessors for different data widths
+///
+/// Which I/O methods are available depends on which [`IoCapable<T>`] traits
+/// are implemented for the type.
+///
+/// # Examples
+///
+/// For MMIO regions, all widths (u8, u16, u32, and u64 on 64-bit systems) are typically
+/// supported. For PCI configuration space, u8, u16, and u32 are supported but u64 is not.
+pub trait Io {
/// Returns the base address of this mapping.
- #[inline]
- pub fn addr(&self) -> usize {
- self.0.addr()
- }
+ fn addr(&self) -> usize;
/// Returns the maximum size of this mapping.
- #[inline]
- pub fn maxsize(&self) -> usize {
- self.0.maxsize()
- }
-
- #[inline]
- const fn offset_valid<U>(offset: usize, size: usize) -> bool {
- let type_size = core::mem::size_of::<U>();
- if let Some(end) = offset.checked_add(type_size) {
- end <= size && offset % type_size == 0
- } else {
- false
- }
- }
+ fn maxsize(&self) -> usize;
+ /// Returns the absolute I/O address for a given `offset`,
+ /// performing runtime bound checks.
#[inline]
fn io_addr<U>(&self, offset: usize) -> Result<usize> {
- if !Self::offset_valid::<U>(offset, self.maxsize()) {
+ if !offset_valid::<U>(offset, self.maxsize()) {
return Err(EINVAL);
}
@@ -241,51 +320,289 @@ impl<const SIZE: usize> Io<SIZE> {
self.addr().checked_add(offset).ok_or(EINVAL)
}
+ /// Fallible 8-bit read with runtime bounds check.
+ #[inline(always)]
+ fn try_read8(&self, _offset: usize) -> Result<u8>
+ where
+ Self: IoCapable<u8>,
+ {
+ build_error!("Backend does not support fallible 8-bit read")
+ }
+
+ /// Fallible 16-bit read with runtime bounds check.
+ #[inline(always)]
+ fn try_read16(&self, _offset: usize) -> Result<u16>
+ where
+ Self: IoCapable<u16>,
+ {
+ build_error!("Backend does not support fallible 16-bit read")
+ }
+
+ /// Fallible 32-bit read with runtime bounds check.
+ #[inline(always)]
+ fn try_read32(&self, _offset: usize) -> Result<u32>
+ where
+ Self: IoCapable<u32>,
+ {
+ build_error!("Backend does not support fallible 32-bit read")
+ }
+
+ /// Fallible 64-bit read with runtime bounds check.
+ #[inline(always)]
+ fn try_read64(&self, _offset: usize) -> Result<u64>
+ where
+ Self: IoCapable<u64>,
+ {
+ build_error!("Backend does not support fallible 64-bit read")
+ }
+
+ /// Fallible 8-bit write with runtime bounds check.
+ #[inline(always)]
+ fn try_write8(&self, _value: u8, _offset: usize) -> Result
+ where
+ Self: IoCapable<u8>,
+ {
+ build_error!("Backend does not support fallible 8-bit write")
+ }
+
+ /// Fallible 16-bit write with runtime bounds check.
+ #[inline(always)]
+ fn try_write16(&self, _value: u16, _offset: usize) -> Result
+ where
+ Self: IoCapable<u16>,
+ {
+ build_error!("Backend does not support fallible 16-bit write")
+ }
+
+ /// Fallible 32-bit write with runtime bounds check.
+ #[inline(always)]
+ fn try_write32(&self, _value: u32, _offset: usize) -> Result
+ where
+ Self: IoCapable<u32>,
+ {
+ build_error!("Backend does not support fallible 32-bit write")
+ }
+
+ /// Fallible 64-bit write with runtime bounds check.
+ #[inline(always)]
+ fn try_write64(&self, _value: u64, _offset: usize) -> Result
+ where
+ Self: IoCapable<u64>,
+ {
+ build_error!("Backend does not support fallible 64-bit write")
+ }
+
+ /// Infallible 8-bit read with compile-time bounds check.
+ #[inline(always)]
+ fn read8(&self, _offset: usize) -> u8
+ where
+ Self: IoKnownSize + IoCapable<u8>,
+ {
+ build_error!("Backend does not support infallible 8-bit read")
+ }
+
+ /// Infallible 16-bit read with compile-time bounds check.
+ #[inline(always)]
+ fn read16(&self, _offset: usize) -> u16
+ where
+ Self: IoKnownSize + IoCapable<u16>,
+ {
+ build_error!("Backend does not support infallible 16-bit read")
+ }
+
+ /// Infallible 32-bit read with compile-time bounds check.
+ #[inline(always)]
+ fn read32(&self, _offset: usize) -> u32
+ where
+ Self: IoKnownSize + IoCapable<u32>,
+ {
+ build_error!("Backend does not support infallible 32-bit read")
+ }
+
+ /// Infallible 64-bit read with compile-time bounds check.
+ #[inline(always)]
+ fn read64(&self, _offset: usize) -> u64
+ where
+ Self: IoKnownSize + IoCapable<u64>,
+ {
+ build_error!("Backend does not support infallible 64-bit read")
+ }
+
+ /// Infallible 8-bit write with compile-time bounds check.
+ #[inline(always)]
+ fn write8(&self, _value: u8, _offset: usize)
+ where
+ Self: IoKnownSize + IoCapable<u8>,
+ {
+ build_error!("Backend does not support infallible 8-bit write")
+ }
+
+ /// Infallible 16-bit write with compile-time bounds check.
+ #[inline(always)]
+ fn write16(&self, _value: u16, _offset: usize)
+ where
+ Self: IoKnownSize + IoCapable<u16>,
+ {
+ build_error!("Backend does not support infallible 16-bit write")
+ }
+
+ /// Infallible 32-bit write with compile-time bounds check.
+ #[inline(always)]
+ fn write32(&self, _value: u32, _offset: usize)
+ where
+ Self: IoKnownSize + IoCapable<u32>,
+ {
+ build_error!("Backend does not support infallible 32-bit write")
+ }
+
+ /// Infallible 64-bit write with compile-time bounds check.
+ #[inline(always)]
+ fn write64(&self, _value: u64, _offset: usize)
+ where
+ Self: IoKnownSize + IoCapable<u64>,
+ {
+ build_error!("Backend does not support infallible 64-bit write")
+ }
+}
+
+/// Trait for types with a known size at compile time.
+///
+/// This trait is implemented by I/O backends that have a compile-time known size,
+/// enabling the use of infallible I/O accessors with compile-time bounds checking.
+///
+/// Types implementing this trait can use the infallible methods in [`Io`] trait
+/// (e.g., `read8`, `write32`), which require `Self: IoKnownSize` bound.
+pub trait IoKnownSize: Io {
+ /// Minimum usable size of this region.
+ const MIN_SIZE: usize;
+
+ /// Returns the absolute I/O address for a given `offset`,
+ /// performing compile-time bound checks.
// Always inline to optimize out error path of `build_assert`.
#[inline(always)]
fn io_addr_assert<U>(&self, offset: usize) -> usize {
- build_assert!(Self::offset_valid::<U>(offset, SIZE));
+ build_assert!(offset_valid::<U>(offset, Self::MIN_SIZE));
self.addr() + offset
}
+}
+
+// MMIO regions support 8, 16, and 32-bit accesses.
+impl<const SIZE: usize> IoCapable<u8> for Mmio<SIZE> {}
+impl<const SIZE: usize> IoCapable<u16> for Mmio<SIZE> {}
+impl<const SIZE: usize> IoCapable<u32> for Mmio<SIZE> {}
+
+// MMIO regions on 64-bit systems also support 64-bit accesses.
+#[cfg(CONFIG_64BIT)]
+impl<const SIZE: usize> IoCapable<u64> for Mmio<SIZE> {}
- define_read!(read8, try_read8, readb -> u8);
- define_read!(read16, try_read16, readw -> u16);
- define_read!(read32, try_read32, readl -> u32);
+impl<const SIZE: usize> Io for Mmio<SIZE> {
+ /// Returns the base address of this mapping.
+ #[inline]
+ fn addr(&self) -> usize {
+ self.0.addr()
+ }
+
+ /// Returns the maximum size of this mapping.
+ #[inline]
+ fn maxsize(&self) -> usize {
+ self.0.maxsize()
+ }
+
+ define_read!(fallible, try_read8, call_mmio_read(readb) -> u8);
+ define_read!(fallible, try_read16, call_mmio_read(readw) -> u16);
+ define_read!(fallible, try_read32, call_mmio_read(readl) -> u32);
define_read!(
+ fallible,
#[cfg(CONFIG_64BIT)]
- read64,
try_read64,
- readq -> u64
+ call_mmio_read(readq) -> u64
+ );
+
+ define_write!(fallible, try_write8, call_mmio_write(writeb) <- u8);
+ define_write!(fallible, try_write16, call_mmio_write(writew) <- u16);
+ define_write!(fallible, try_write32, call_mmio_write(writel) <- u32);
+ define_write!(
+ fallible,
+ #[cfg(CONFIG_64BIT)]
+ try_write64,
+ call_mmio_write(writeq) <- u64
);
- define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8);
- define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16);
- define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32);
+ define_read!(infallible, read8, call_mmio_read(readb) -> u8);
+ define_read!(infallible, read16, call_mmio_read(readw) -> u16);
+ define_read!(infallible, read32, call_mmio_read(readl) -> u32);
define_read!(
+ infallible,
#[cfg(CONFIG_64BIT)]
- read64_relaxed,
- try_read64_relaxed,
- readq_relaxed -> u64
+ read64,
+ call_mmio_read(readq) -> u64
);
- define_write!(write8, try_write8, writeb <- u8);
- define_write!(write16, try_write16, writew <- u16);
- define_write!(write32, try_write32, writel <- u32);
+ define_write!(infallible, write8, call_mmio_write(writeb) <- u8);
+ define_write!(infallible, write16, call_mmio_write(writew) <- u16);
+ define_write!(infallible, write32, call_mmio_write(writel) <- u32);
define_write!(
+ infallible,
#[cfg(CONFIG_64BIT)]
write64,
- try_write64,
- writeq <- u64
+ call_mmio_write(writeq) <- u64
+ );
+}
+
+impl<const SIZE: usize> IoKnownSize for Mmio<SIZE> {
+ const MIN_SIZE: usize = SIZE;
+}
+
+impl<const SIZE: usize> Mmio<SIZE> {
+ /// Converts an `MmioRaw` into an `Mmio` instance, providing the accessors to the MMIO mapping.
+ ///
+ /// # Safety
+ ///
+ /// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size
+ /// `maxsize`.
+ pub unsafe fn from_raw(raw: &MmioRaw<SIZE>) -> &Self {
+ // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`.
+ unsafe { &*core::ptr::from_ref(raw).cast() }
+ }
+
+ define_read!(infallible, pub read8_relaxed, call_mmio_read(readb_relaxed) -> u8);
+ define_read!(infallible, pub read16_relaxed, call_mmio_read(readw_relaxed) -> u16);
+ define_read!(infallible, pub read32_relaxed, call_mmio_read(readl_relaxed) -> u32);
+ define_read!(
+ infallible,
+ #[cfg(CONFIG_64BIT)]
+ pub read64_relaxed,
+ call_mmio_read(readq_relaxed) -> u64
+ );
+
+ define_read!(fallible, pub try_read8_relaxed, call_mmio_read(readb_relaxed) -> u8);
+ define_read!(fallible, pub try_read16_relaxed, call_mmio_read(readw_relaxed) -> u16);
+ define_read!(fallible, pub try_read32_relaxed, call_mmio_read(readl_relaxed) -> u32);
+ define_read!(
+ fallible,
+ #[cfg(CONFIG_64BIT)]
+ pub try_read64_relaxed,
+ call_mmio_read(readq_relaxed) -> u64
+ );
+
+ define_write!(infallible, pub write8_relaxed, call_mmio_write(writeb_relaxed) <- u8);
+ define_write!(infallible, pub write16_relaxed, call_mmio_write(writew_relaxed) <- u16);
+ define_write!(infallible, pub write32_relaxed, call_mmio_write(writel_relaxed) <- u32);
+ define_write!(
+ infallible,
+ #[cfg(CONFIG_64BIT)]
+ pub write64_relaxed,
+ call_mmio_write(writeq_relaxed) <- u64
);
- define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8);
- define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- u16);
- define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- u32);
+ define_write!(fallible, pub try_write8_relaxed, call_mmio_write(writeb_relaxed) <- u8);
+ define_write!(fallible, pub try_write16_relaxed, call_mmio_write(writew_relaxed) <- u16);
+ define_write!(fallible, pub try_write32_relaxed, call_mmio_write(writel_relaxed) <- u32);
define_write!(
+ fallible,
#[cfg(CONFIG_64BIT)]
- write64_relaxed,
- try_write64_relaxed,
- writeq_relaxed <- u64
+ pub try_write64_relaxed,
+ call_mmio_write(writeq_relaxed) <- u64
);
}
diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs
index b03b82cd531b..620022cff401 100644
--- a/rust/kernel/io/mem.rs
+++ b/rust/kernel/io/mem.rs
@@ -5,7 +5,6 @@
use core::ops::Deref;
use crate::{
- c_str,
device::{
Bound,
Device, //
@@ -17,8 +16,8 @@ use crate::{
Region,
Resource, //
},
- Io,
- IoRaw, //
+ Mmio,
+ MmioRaw, //
},
prelude::*,
};
@@ -52,7 +51,12 @@ impl<'a> IoRequest<'a> {
/// illustration purposes.
///
/// ```no_run
- /// use kernel::{bindings, c_str, platform, of, device::Core};
+ /// use kernel::{
+ /// bindings,
+ /// device::Core,
+ /// of,
+ /// platform,
+ /// };
/// struct SampleDriver;
///
/// impl platform::Driver for SampleDriver {
@@ -110,7 +114,12 @@ impl<'a> IoRequest<'a> {
/// illustration purposes.
///
/// ```no_run
- /// use kernel::{bindings, c_str, platform, of, device::Core};
+ /// use kernel::{
+ /// bindings,
+ /// device::Core,
+ /// of,
+ /// platform,
+ /// };
/// struct SampleDriver;
///
/// impl platform::Driver for SampleDriver {
@@ -172,7 +181,7 @@ impl<const SIZE: usize> ExclusiveIoMem<SIZE> {
fn ioremap(resource: &Resource) -> Result<Self> {
let start = resource.start();
let size = resource.size();
- let name = resource.name().unwrap_or(c_str!(""));
+ let name = resource.name().unwrap_or_default();
let region = resource
.request_region(
@@ -203,7 +212,7 @@ impl<const SIZE: usize> ExclusiveIoMem<SIZE> {
}
impl<const SIZE: usize> Deref for ExclusiveIoMem<SIZE> {
- type Target = Io<SIZE>;
+ type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
&self.iomem
@@ -217,10 +226,10 @@ impl<const SIZE: usize> Deref for ExclusiveIoMem<SIZE> {
///
/// # Invariants
///
-/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointer to the
+/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid pointer to the
/// start of the I/O memory mapped region.
pub struct IoMem<const SIZE: usize = 0> {
- io: IoRaw<SIZE>,
+ io: MmioRaw<SIZE>,
}
impl<const SIZE: usize> IoMem<SIZE> {
@@ -255,7 +264,7 @@ impl<const SIZE: usize> IoMem<SIZE> {
return Err(ENOMEM);
}
- let io = IoRaw::new(addr as usize, size)?;
+ let io = MmioRaw::new(addr as usize, size)?;
let io = IoMem { io };
Ok(io)
@@ -278,10 +287,10 @@ impl<const SIZE: usize> Drop for IoMem<SIZE> {
}
impl<const SIZE: usize> Deref for IoMem<SIZE> {
- type Target = Io<SIZE>;
+ type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
// SAFETY: Safe as by the invariant of `IoMem`.
- unsafe { Io::from_raw(&self.io) }
+ unsafe { Mmio::from_raw(&self.io) }
}
}
diff --git a/rust/kernel/io/poll.rs b/rust/kernel/io/poll.rs
index b1a2570364f4..75d1b3e8596c 100644
--- a/rust/kernel/io/poll.rs
+++ b/rust/kernel/io/poll.rs
@@ -45,12 +45,16 @@ use crate::{
/// # Examples
///
/// ```no_run
-/// use kernel::io::{Io, poll::read_poll_timeout};
+/// use kernel::io::{
+/// Io,
+/// Mmio,
+/// poll::read_poll_timeout, //
+/// };
/// use kernel::time::Delta;
///
/// const HW_READY: u16 = 0x01;
///
-/// fn wait_for_hardware<const SIZE: usize>(io: &Io<SIZE>) -> Result {
+/// fn wait_for_hardware<const SIZE: usize>(io: &Mmio<SIZE>) -> Result {
/// read_poll_timeout(
/// // The `op` closure reads the value of a specific status register.
/// || io.try_read16(0x1000),
@@ -128,12 +132,16 @@ where
/// # Examples
///
/// ```no_run
-/// use kernel::io::{poll::read_poll_timeout_atomic, Io};
+/// use kernel::io::{
+/// Io,
+/// Mmio,
+/// poll::read_poll_timeout_atomic, //
+/// };
/// use kernel::time::Delta;
///
/// const HW_READY: u16 = 0x01;
///
-/// fn wait_for_hardware<const SIZE: usize>(io: &Io<SIZE>) -> Result {
+/// fn wait_for_hardware<const SIZE: usize>(io: &Mmio<SIZE>) -> Result {
/// read_poll_timeout_atomic(
/// // The `op` closure reads the value of a specific status register.
/// || io.try_read16(0x1000),
diff --git a/rust/kernel/irq/request.rs b/rust/kernel/irq/request.rs
index b150563fdef8..67769800117c 100644
--- a/rust/kernel/irq/request.rs
+++ b/rust/kernel/irq/request.rs
@@ -139,7 +139,6 @@ impl<'a> IrqRequest<'a> {
/// [`Completion::wait_for_completion()`]: kernel::sync::Completion::wait_for_completion
///
/// ```
-/// use kernel::c_str;
/// use kernel::device::{Bound, Device};
/// use kernel::irq::{self, Flags, IrqRequest, IrqReturn, Registration};
/// use kernel::prelude::*;
@@ -167,7 +166,7 @@ impl<'a> IrqRequest<'a> {
/// handler: impl PinInit<Data, Error>,
/// request: IrqRequest<'_>,
/// ) -> Result<Arc<Registration<Data>>> {
-/// let registration = Registration::new(request, Flags::SHARED, c_str!("my_device"), handler);
+/// let registration = Registration::new(request, Flags::SHARED, c"my_device", handler);
///
/// let registration = Arc::pin_init(registration, GFP_KERNEL)?;
///
@@ -340,7 +339,6 @@ impl<T: ?Sized + ThreadedHandler, A: Allocator> ThreadedHandler for Box<T, A> {
/// [`Mutex`](kernel::sync::Mutex) to provide interior mutability.
///
/// ```
-/// use kernel::c_str;
/// use kernel::device::{Bound, Device};
/// use kernel::irq::{
/// self, Flags, IrqRequest, IrqReturn, ThreadedHandler, ThreadedIrqReturn,
@@ -381,7 +379,7 @@ impl<T: ?Sized + ThreadedHandler, A: Allocator> ThreadedHandler for Box<T, A> {
/// request: IrqRequest<'_>,
/// ) -> Result<Arc<ThreadedRegistration<Data>>> {
/// let registration =
-/// ThreadedRegistration::new(request, Flags::SHARED, c_str!("my_device"), handler);
+/// ThreadedRegistration::new(request, Flags::SHARED, c"my_device", handler);
///
/// let registration = Arc::pin_init(registration, GFP_KERNEL)?;
///
diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs
index 0f4ceebb031d..3da92f18f4ee 100644
--- a/rust/kernel/lib.rs
+++ b/rust/kernel/lib.rs
@@ -142,6 +142,8 @@ pub mod security;
pub mod seq_file;
pub mod sizes;
pub mod slice;
+#[cfg(CONFIG_SOC_BUS)]
+pub mod soc;
mod static_assert;
#[doc(hidden)]
pub mod std_vendor;
diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
index bea76ca9c3da..af74ddff6114 100644
--- a/rust/kernel/pci.rs
+++ b/rust/kernel/pci.rs
@@ -40,7 +40,14 @@ pub use self::id::{
ClassMask,
Vendor, //
};
-pub use self::io::Bar;
+pub use self::io::{
+ Bar,
+ ConfigSpace,
+ ConfigSpaceKind,
+ ConfigSpaceSize,
+ Extended,
+ Normal, //
+};
pub use self::irq::{
IrqType,
IrqTypes,
@@ -351,7 +358,7 @@ impl Device {
/// // Get an instance of `Vendor`.
/// let vendor = pdev.vendor_id();
/// dev_info!(
- /// pdev.as_ref(),
+ /// pdev,
/// "Device: Vendor={}, Device=0x{:x}\n",
/// vendor,
/// pdev.device_id()
diff --git a/rust/kernel/pci/id.rs b/rust/kernel/pci/id.rs
index c09125946d9e..e2d9e8804347 100644
--- a/rust/kernel/pci/id.rs
+++ b/rust/kernel/pci/id.rs
@@ -22,7 +22,7 @@ use crate::{
/// fn probe_device(pdev: &pci::Device<Core>) -> Result {
/// let pci_class = pdev.pci_class();
/// dev_info!(
-/// pdev.as_ref(),
+/// pdev,
/// "Detected PCI class: {}\n",
/// pci_class
/// );
diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs
index 82a4f1eba2f5..6ca4cf75594c 100644
--- a/rust/kernel/pci/io.rs
+++ b/rust/kernel/pci/io.rs
@@ -8,23 +8,186 @@ use crate::{
device,
devres::Devres,
io::{
+ define_read,
+ define_write,
Io,
- IoRaw, //
+ IoCapable,
+ IoKnownSize,
+ Mmio,
+ MmioRaw, //
},
prelude::*,
sync::aref::ARef, //
};
-use core::ops::Deref;
+use core::{
+ marker::PhantomData,
+ ops::Deref, //
+};
+
+/// Represents the size of a PCI configuration space.
+///
+/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
+/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
+/// specification.
+#[repr(usize)]
+#[derive(Eq, PartialEq)]
+pub enum ConfigSpaceSize {
+ /// 256-byte legacy PCI configuration space.
+ Normal = 256,
+
+ /// 4096-byte PCIe extended configuration space.
+ Extended = 4096,
+}
+
+impl ConfigSpaceSize {
+ /// Get the raw value of this enum.
+ #[inline(always)]
+ pub const fn into_raw(self) -> usize {
+ // CAST: PCI configuration space size is at most 4096 bytes, so the value always fits
+ // within `usize` without truncation or sign change.
+ self as usize
+ }
+}
+
+/// Marker type for normal (256-byte) PCI configuration space.
+pub struct Normal;
+
+/// Marker type for extended (4096-byte) PCIe configuration space.
+pub struct Extended;
+
+/// Trait for PCI configuration space size markers.
+///
+/// This trait is implemented by [`Normal`] and [`Extended`] to provide
+/// compile-time knowledge of the configuration space size.
+pub trait ConfigSpaceKind {
+ /// The size of this configuration space in bytes.
+ const SIZE: usize;
+}
+
+impl ConfigSpaceKind for Normal {
+ const SIZE: usize = 256;
+}
+
+impl ConfigSpaceKind for Extended {
+ const SIZE: usize = 4096;
+}
+
+/// The PCI configuration space of a device.
+///
+/// Provides typed read and write accessors for configuration registers
+/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
+///
+/// The generic parameter `S` indicates the maximum size of the configuration space.
+/// Use [`Normal`] for 256-byte legacy configuration space or [`Extended`] for
+/// 4096-byte PCIe extended configuration space (default).
+pub struct ConfigSpace<'a, S: ConfigSpaceKind = Extended> {
+ pub(crate) pdev: &'a Device<device::Bound>,
+ _marker: PhantomData<S>,
+}
+
+/// Internal helper macros used to invoke C PCI configuration space read functions.
+///
+/// This macro is intended to be used by higher-level PCI configuration space access macros
+/// (define_read) and provides a unified expansion for infallible vs. fallible read semantics. It
+/// emits a direct call into the corresponding C helper and performs the required cast to the Rust
+/// return type.
+///
+/// # Parameters
+///
+/// * `$c_fn` – The C function performing the PCI configuration space write.
+/// * `$self` – The I/O backend object.
+/// * `$ty` – The type of the value to read.
+/// * `$addr` – The PCI configuration space offset to read.
+///
+/// This macro does not perform any validation; all invariants must be upheld by the higher-level
+/// abstraction invoking it.
+macro_rules! call_config_read {
+ (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
+ let mut val: $ty = 0;
+ // SAFETY: By the type invariant `$self.pdev` is a valid address.
+ // CAST: The offset is cast to `i32` because the C functions expect a 32-bit signed offset
+ // parameter. PCI configuration space size is at most 4096 bytes, so the value always fits
+ // within `i32` without truncation or sign change.
+ // Return value from C function is ignored in infallible accessors.
+ let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, &mut val) };
+ val
+ }};
+}
+
+/// Internal helper macros used to invoke C PCI configuration space write functions.
+///
+/// This macro is intended to be used by higher-level PCI configuration space access macros
+/// (define_write) and provides a unified expansion for infallible vs. fallible read semantics. It
+/// emits a direct call into the corresponding C helper and performs the required cast to the Rust
+/// return type.
+///
+/// # Parameters
+///
+/// * `$c_fn` – The C function performing the PCI configuration space write.
+/// * `$self` – The I/O backend object.
+/// * `$ty` – The type of the written value.
+/// * `$addr` – The configuration space offset to write.
+/// * `$value` – The value to write.
+///
+/// This macro does not perform any validation; all invariants must be upheld by the higher-level
+/// abstraction invoking it.
+macro_rules! call_config_write {
+ (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
+ // SAFETY: By the type invariant `$self.pdev` is a valid address.
+ // CAST: The offset is cast to `i32` because the C functions expect a 32-bit signed offset
+ // parameter. PCI configuration space size is at most 4096 bytes, so the value always fits
+ // within `i32` without truncation or sign change.
+ // Return value from C function is ignored in infallible accessors.
+ let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, $value) };
+ };
+}
+
+// PCI configuration space supports 8, 16, and 32-bit accesses.
+impl<'a, S: ConfigSpaceKind> IoCapable<u8> for ConfigSpace<'a, S> {}
+impl<'a, S: ConfigSpaceKind> IoCapable<u16> for ConfigSpace<'a, S> {}
+impl<'a, S: ConfigSpaceKind> IoCapable<u32> for ConfigSpace<'a, S> {}
+
+impl<'a, S: ConfigSpaceKind> Io for ConfigSpace<'a, S> {
+ /// Returns the base address of the I/O region. It is always 0 for configuration space.
+ #[inline]
+ fn addr(&self) -> usize {
+ 0
+ }
+
+ /// Returns the maximum size of the configuration space.
+ #[inline]
+ fn maxsize(&self) -> usize {
+ self.pdev.cfg_size().into_raw()
+ }
+
+ // PCI configuration space does not support fallible operations.
+ // The default implementations from the Io trait are not used.
+
+ define_read!(infallible, read8, call_config_read(pci_read_config_byte) -> u8);
+ define_read!(infallible, read16, call_config_read(pci_read_config_word) -> u16);
+ define_read!(infallible, read32, call_config_read(pci_read_config_dword) -> u32);
+
+ define_write!(infallible, write8, call_config_write(pci_write_config_byte) <- u8);
+ define_write!(infallible, write16, call_config_write(pci_write_config_word) <- u16);
+ define_write!(infallible, write32, call_config_write(pci_write_config_dword) <- u32);
+}
+
+impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> {
+ const MIN_SIZE: usize = S::SIZE;
+}
/// A PCI BAR to perform I/O-Operations on.
///
+/// I/O backend assumes that the device is little-endian and will automatically
+/// convert from little-endian to CPU endianness.
+///
/// # Invariants
///
/// `Bar` always holds an `IoRaw` instance that holds a valid pointer to the start of the I/O
/// memory mapped PCI BAR and its size.
pub struct Bar<const SIZE: usize = 0> {
pdev: ARef<Device>,
- io: IoRaw<SIZE>,
+ io: MmioRaw<SIZE>,
num: i32,
}
@@ -60,7 +223,7 @@ impl<const SIZE: usize> Bar<SIZE> {
return Err(ENOMEM);
}
- let io = match IoRaw::new(ioptr, len as usize) {
+ let io = match MmioRaw::new(ioptr, len as usize) {
Ok(io) => io,
Err(err) => {
// SAFETY:
@@ -114,11 +277,11 @@ impl<const SIZE: usize> Drop for Bar<SIZE> {
}
impl<const SIZE: usize> Deref for Bar<SIZE> {
- type Target = Io<SIZE>;
+ type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
// SAFETY: By the type invariant of `Self`, the MMIO range in `self.io` is properly mapped.
- unsafe { Io::from_raw(&self.io) }
+ unsafe { Mmio::from_raw(&self.io) }
}
}
@@ -141,4 +304,39 @@ impl Device<device::Bound> {
) -> impl PinInit<Devres<Bar>, Error> + 'a {
self.iomap_region_sized::<0>(bar, name)
}
+
+ /// Returns the size of configuration space.
+ pub fn cfg_size(&self) -> ConfigSpaceSize {
+ // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
+ let size = unsafe { (*self.as_raw()).cfg_size };
+ match size {
+ 256 => ConfigSpaceSize::Normal,
+ 4096 => ConfigSpaceSize::Extended,
+ _ => {
+ // PANIC: The PCI subsystem only ever reports the configuration space size as either
+ // `ConfigSpaceSize::Normal` or `ConfigSpaceSize::Extended`.
+ unreachable!();
+ }
+ }
+ }
+
+ /// Return an initialized normal (256-byte) config space object.
+ pub fn config_space<'a>(&'a self) -> ConfigSpace<'a, Normal> {
+ ConfigSpace {
+ pdev: self,
+ _marker: PhantomData,
+ }
+ }
+
+ /// Return an initialized extended (4096-byte) config space object.
+ pub fn config_space_extended<'a>(&'a self) -> Result<ConfigSpace<'a, Extended>> {
+ if self.cfg_size() != ConfigSpaceSize::Extended {
+ return Err(EINVAL);
+ }
+
+ Ok(ConfigSpace {
+ pdev: self,
+ _marker: PhantomData,
+ })
+ }
}
diff --git a/rust/kernel/platform.rs b/rust/kernel/platform.rs
index 35a5813ffb33..8917d4ee499f 100644
--- a/rust/kernel/platform.rs
+++ b/rust/kernel/platform.rs
@@ -5,22 +5,39 @@
//! C header: [`include/linux/platform_device.h`](srctree/include/linux/platform_device.h)
use crate::{
- acpi, bindings, container_of,
- device::{self, Bound},
+ acpi,
+ bindings,
+ container_of,
+ device::{
+ self,
+ Bound, //
+ },
driver,
- error::{from_result, to_result, Result},
- io::{mem::IoRequest, Resource},
- irq::{self, IrqRequest},
+ error::{
+ from_result,
+ to_result, //
+ },
+ io::{
+ mem::IoRequest,
+ Resource, //
+ },
+ irq::{
+ self,
+ IrqRequest, //
+ },
of,
prelude::*,
types::Opaque,
- ThisModule,
+ ThisModule, //
};
use core::{
marker::PhantomData,
mem::offset_of,
- ptr::{addr_of_mut, NonNull},
+ ptr::{
+ addr_of_mut,
+ NonNull, //
+ },
};
/// An adapter for the registration of platform drivers.
@@ -95,7 +112,7 @@ impl<T: Driver + 'static> Adapter<T> {
// SAFETY: The platform bus only ever calls the remove callback with a valid pointer to a
// `struct platform_device`.
//
- // INVARIANT: `pdev` is valid for the duration of `probe_callback()`.
+ // INVARIANT: `pdev` is valid for the duration of `remove_callback()`.
let pdev = unsafe { &*pdev.cast::<Device<device::CoreInternal>>() };
// SAFETY: `remove_callback` is only ever called after a successful call to
@@ -146,8 +163,13 @@ macro_rules! module_platform_driver {
/// # Examples
///
///```
-/// # use kernel::{acpi, bindings, c_str, device::Core, of, platform};
-///
+/// # use kernel::{
+/// # acpi,
+/// # bindings,
+/// # device::Core,
+/// # of,
+/// # platform,
+/// # };
/// struct MyDriver;
///
/// kernel::of_device_table!(
@@ -155,7 +177,7 @@ macro_rules! module_platform_driver {
/// MODULE_OF_TABLE,
/// <MyDriver as platform::Driver>::IdInfo,
/// [
-/// (of::DeviceId::new(c_str!("test,device")), ())
+/// (of::DeviceId::new(c"test,device"), ())
/// ]
/// );
///
@@ -164,7 +186,7 @@ macro_rules! module_platform_driver {
/// MODULE_ACPI_TABLE,
/// <MyDriver as platform::Driver>::IdInfo,
/// [
-/// (acpi::DeviceId::new(c_str!("LNUXBEEF")), ())
+/// (acpi::DeviceId::new(c"LNUXBEEF"), ())
/// ]
/// );
///
diff --git a/rust/kernel/scatterlist.rs b/rust/kernel/scatterlist.rs
index 196fdb9a75e7..b83c468b5c63 100644
--- a/rust/kernel/scatterlist.rs
+++ b/rust/kernel/scatterlist.rs
@@ -38,7 +38,8 @@ use crate::{
io::ResourceSize,
page,
prelude::*,
- types::{ARef, Opaque},
+ sync::aref::ARef,
+ types::Opaque,
};
use core::{ops::Deref, ptr::NonNull};
diff --git a/rust/kernel/soc.rs b/rust/kernel/soc.rs
new file mode 100644
index 000000000000..0d6a36c83cb6
--- /dev/null
+++ b/rust/kernel/soc.rs
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! SoC Driver Abstraction.
+//!
+//! C header: [`include/linux/sys_soc.h`](srctree/include/linux/sys_soc.h)
+
+use crate::{
+ bindings,
+ error,
+ prelude::*,
+ str::CString,
+ types::Opaque, //
+};
+use core::ptr::NonNull;
+
+/// Attributes for a SoC device.
+///
+/// These are both exported to userspace under /sys/devices/socX and provided to other drivers to
+/// match against via `soc_device_match` (not yet available in Rust) to enable quirks or
+/// device-specific support where necessary.
+///
+/// All fields are freeform - they have no specific formatting, just defined meanings.
+/// For example, the [`machine`](`Attributes::machine`) field could be "DB8500" or
+/// "Qualcomm Technologies, Inc. SM8560 HDK", but regardless it should identify a board or product.
+pub struct Attributes {
+ /// Should generally be a board ID or product ID. Examples
+ /// include DB8500 (ST-Ericsson) or "Qualcomm Technologies, inc. SM8560 HDK".
+ ///
+ /// If this field is not populated, the SoC infrastructure will try to populate it from
+ /// `/model` in the device tree.
+ pub machine: Option<CString>,
+ /// The broader class this SoC belongs to. Examples include ux500
+ /// (for DB8500) or Snapdragon (for SM8650).
+ ///
+ /// On chips with ARM firmware supporting SMCCC v1.2+, this may be a JEDEC JEP106 manufacturer
+ /// identification.
+ pub family: Option<CString>,
+ /// The manufacturing revision of the part. Frequently this is MAJOR.MINOR, but not always.
+ pub revision: Option<CString>,
+ /// Serial Number - uniquely identifies a specific SoC. If present, should be unique (buying a
+ /// replacement part should change it if present). This field cannot be matched on and is
+ /// solely present to export through /sys.
+ pub serial_number: Option<CString>,
+ /// SoC ID - identifies a specific SoC kind in question, sometimes more specifically than
+ /// `machine` if the same SoC is used in multiple products. Some devices use this to specify a
+ /// SoC name, e.g. "I.MX??", and others just print an ID number (e.g. Tegra and Qualcomm).
+ ///
+ /// On chips with ARM firmware supporting SMCCC v1.2+, this may be a JEDEC JEP106 manufacturer
+ /// identification (the family value) followed by a colon and then a 4-digit ID value.
+ pub soc_id: Option<CString>,
+}
+
+struct BuiltAttributes {
+ // While `inner` has pointers to `_backing`, it is to the interior of the `CStrings`, not
+ // `backing` itself, so it does not need to be pinned.
+ _backing: Attributes,
+ // `Opaque` makes us `!Unpin`, as the registration holds a pointer to `inner` when used.
+ inner: Opaque<bindings::soc_device_attribute>,
+}
+
+fn cstring_to_c(mcs: &Option<CString>) -> *const kernel::ffi::c_char {
+ mcs.as_ref()
+ .map(|cs| cs.as_char_ptr())
+ .unwrap_or(core::ptr::null())
+}
+
+impl BuiltAttributes {
+ fn as_mut_ptr(&self) -> *mut bindings::soc_device_attribute {
+ self.inner.get()
+ }
+}
+
+impl Attributes {
+ fn build(self) -> BuiltAttributes {
+ BuiltAttributes {
+ inner: Opaque::new(bindings::soc_device_attribute {
+ machine: cstring_to_c(&self.machine),
+ family: cstring_to_c(&self.family),
+ revision: cstring_to_c(&self.revision),
+ serial_number: cstring_to_c(&self.serial_number),
+ soc_id: cstring_to_c(&self.soc_id),
+ data: core::ptr::null(),
+ custom_attr_group: core::ptr::null(),
+ }),
+ _backing: self,
+ }
+ }
+}
+
+#[pin_data(PinnedDrop)]
+/// Registration handle for your soc_dev. If you let it go out of scope, your soc_dev will be
+/// unregistered.
+pub struct Registration {
+ #[pin]
+ attr: BuiltAttributes,
+ soc_dev: NonNull<bindings::soc_device>,
+}
+
+// SAFETY: We provide no operations through `&Registration`.
+unsafe impl Sync for Registration {}
+
+// SAFETY: All pointers are normal allocations, not thread-specific.
+unsafe impl Send for Registration {}
+
+#[pinned_drop]
+impl PinnedDrop for Registration {
+ fn drop(self: Pin<&mut Self>) {
+ // SAFETY: Device always contains a live pointer to a soc_device that can be unregistered
+ unsafe { bindings::soc_device_unregister(self.soc_dev.as_ptr()) }
+ }
+}
+
+impl Registration {
+ /// Register a new SoC device
+ pub fn new(attr: Attributes) -> impl PinInit<Self, Error> {
+ try_pin_init!(Self {
+ attr: attr.build(),
+ soc_dev: {
+ // SAFETY:
+ // * The struct provided through attr is backed by pinned data next to it,
+ // so as long as attr lives, the strings pointed to by the struct will too.
+ // * `attr` is pinned, so the pinned data won't move.
+ // * If it returns a device, and so others may try to read this data, by
+ // caller invariant, `attr` won't be released until the device is.
+ let raw_soc = error::from_err_ptr(unsafe {
+ bindings::soc_device_register(attr.as_mut_ptr())
+ })?;
+
+ NonNull::new(raw_soc).ok_or(EINVAL)?
+ },
+ }? Error)
+ }
+}