diff options
Diffstat (limited to 'drivers/soc/qcom')
| -rw-r--r-- | drivers/soc/qcom/Kconfig | 108 | ||||
| -rw-r--r-- | drivers/soc/qcom/llcc-qcom.c | 29 | ||||
| -rw-r--r-- | drivers/soc/qcom/mdt_loader.c | 12 | ||||
| -rw-r--r-- | drivers/soc/qcom/qcom_pd_mapper.c | 38 | ||||
| -rw-r--r-- | drivers/soc/qcom/qcom_stats.c | 2 | ||||
| -rw-r--r-- | drivers/soc/qcom/rpmh-rsc.c | 37 | ||||
| -rw-r--r-- | drivers/soc/qcom/ubwc_config.c | 1 |
7 files changed, 167 insertions, 60 deletions
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index f6970431d07d..fd4d4ecd2df0 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -2,14 +2,25 @@ # # QCOM Soc drivers # -menu "Qualcomm SoC drivers" +menuconfig QCOM_SOC + bool "Qualcomm SoC drivers" + depends on ARCH_QCOM || COMPILE_TEST + default ARCH_QCOM + help + This collection of drivers is specific to Qualcomm System-on-Chips + and most of them are necessary for a fully functional boot of the + Linux kernel (plus a few debugging drivers). + Drivers can be skipped when building Linux kernel not intended to run + said processors. + +if QCOM_SOC config QCOM_AOSS_QMP tristate "Qualcomm AOSS Driver" - depends on ARCH_QCOM || COMPILE_TEST depends on MAILBOX depends on COMMON_CLK && PM select PM_GENERIC_DOMAINS + default ARCH_QCOM help This driver provides the means of communicating with and controlling the low-power state for resources related to the remoteproc @@ -18,8 +29,8 @@ config QCOM_AOSS_QMP config QCOM_COMMAND_DB tristate "Qualcomm Command DB" - depends on ARCH_QCOM || COMPILE_TEST depends on OF_RESERVED_MEM + default ARCH_QCOM help Command DB queries shared memory by key string for shared system resources. Platform drivers that require to set state of a shared @@ -28,7 +39,8 @@ config QCOM_COMMAND_DB config QCOM_GENI_SE tristate "Qualcomm GENI Serial Engine Driver" - depends on ARCH_QCOM || COMPILE_TEST + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This driver is used to manage Generic Interface (GENI) firmware based Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This @@ -37,7 +49,8 @@ config QCOM_GENI_SE config QCOM_GSBI tristate "Qualcomm General Serial Bus Interface" - depends on ARCH_QCOM || COMPILE_TEST + depends on ARM || COMPILE_TEST + default ARCH_QCOM select MFD_SYSCON help Say y here to enable GSBI support. The GSBI provides control @@ -46,26 +59,18 @@ config QCOM_GSBI config QCOM_LLCC tristate "Qualcomm LLCC driver" - depends on ARCH_QCOM || COMPILE_TEST select REGMAP_MMIO + default m if ARCH_QCOM help Qualcomm Technologies, Inc. platform specific Last Level Cache Controller(LLCC) driver for platforms such as, SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. -config QCOM_KRYO_L2_ACCESSORS - bool - depends on (ARCH_QCOM || COMPILE_TEST) && ARM64 - -config QCOM_MDT_LOADER - tristate - select QCOM_SCM - config QCOM_OCMEM tristate "Qualcomm On Chip Memory (OCMEM) driver" - depends on ARCH_QCOM select QCOM_SCM + default m if ARCH_QCOM help The On Chip Memory (OCMEM) allocator allows various clients to allocate memory from OCMEM based on performance, latency and power @@ -77,7 +82,7 @@ config QCOM_PD_MAPPER select QCOM_QMI_HELPERS select QCOM_PDR_MSG select AUXILIARY_BUS - depends on NET && QRTR && (ARCH_QCOM || COMPILE_TEST) + depends on NET && QRTR default QCOM_RPROC_COMMON help The Protection Domain Mapper maps registered services to the domains @@ -85,12 +90,6 @@ config QCOM_PD_MAPPER implementation of the service. It is a simpler alternative to the userspace daemon. -config QCOM_PDR_HELPERS - tristate - select QCOM_QMI_HELPERS - select QCOM_PDR_MSG - depends on NET - config QCOM_PDR_MSG tristate @@ -113,9 +112,11 @@ config QCOM_PMIC_GLINK depends on DRM depends on NET depends on OF + depends on ARM64 || COMPILE_TEST select AUXILIARY_BUS select QCOM_PDR_HELPERS select DRM_AUX_HPD_BRIDGE + default m if ARCH_QCOM help The Qualcomm PMIC GLINK driver provides access, over GLINK, to the USB and battery firmware running on one of the coprocessors in @@ -124,13 +125,8 @@ config QCOM_PMIC_GLINK Say yes here to support USB-C and battery status on modern Qualcomm platforms. -config QCOM_QMI_HELPERS - tristate - depends on NET - config QCOM_RAMP_CTRL tristate "Qualcomm Ramp Controller driver" - depends on ARCH_QCOM || COMPILE_TEST help The Ramp Controller is used to program the sequence ID for pulse swallowing, enable sequence and link sequence IDs for the CPU @@ -139,8 +135,8 @@ config QCOM_RAMP_CTRL config QCOM_RMTFS_MEM tristate "Qualcomm Remote Filesystem memory driver" - depends on ARCH_QCOM || COMPILE_TEST select QCOM_SCM + default m if ARCH_QCOM help The Qualcomm remote filesystem memory driver is used for allocating and exposing regions of shared memory with remote processors for the @@ -151,7 +147,6 @@ config QCOM_RMTFS_MEM config QCOM_RPM_MASTER_STATS tristate "Qualcomm RPM Master stats" - depends on ARCH_QCOM || COMPILE_TEST help The RPM Master sleep stats driver provides detailed per-subsystem sleep/wake data, read from the RPM message RAM. It can be used to @@ -162,8 +157,8 @@ config QCOM_RPM_MASTER_STATS config QCOM_RPMH tristate "Qualcomm RPM-Hardened (RPMH) Communication" - depends on ARCH_QCOM || COMPILE_TEST depends on (QCOM_COMMAND_DB || !QCOM_COMMAND_DB) + default ARCH_QCOM help Support for communication with the hardened-RPM blocks in Qualcomm Technologies Inc (QTI) SoCs. RPMH communication uses an @@ -173,8 +168,8 @@ config QCOM_RPMH config QCOM_SMEM tristate "Qualcomm Shared Memory Manager (SMEM)" - depends on ARCH_QCOM || COMPILE_TEST depends on HWSPINLOCK + default ARCH_QCOM help Say y here to enable support for the Qualcomm Shared Memory Manager. The driver provides an interface to items in a heap shared among all @@ -182,9 +177,9 @@ config QCOM_SMEM config QCOM_SMD_RPM tristate "Qualcomm Resource Power Manager (RPM) over SMD" - depends on ARCH_QCOM || COMPILE_TEST depends on RPMSG depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n + default ARCH_QCOM help If you say yes to this option, support will be included for the Resource Power Manager system found in the Qualcomm 8974 based @@ -205,6 +200,7 @@ config QCOM_SMP2P depends on QCOM_SMEM select QCOM_SMEM_STATE select IRQ_DOMAIN + default ARCH_QCOM help Say yes here to support the Qualcomm Shared Memory Point to Point protocol. @@ -215,6 +211,7 @@ config QCOM_SMSM depends on QCOM_SMEM select QCOM_SMEM_STATE select IRQ_DOMAIN + default ARCH_QCOM help Say yes here to support the Qualcomm Shared Memory State Machine. The state machine is represented by bits in shared memory. @@ -223,14 +220,15 @@ config QCOM_SOCINFO tristate "Qualcomm socinfo driver" depends on QCOM_SMEM select SOC_BUS + default m if ARCH_QCOM help Say yes here to support the Qualcomm socinfo driver, providing information about the SoC to user space. config QCOM_SPM tristate "Qualcomm Subsystem Power Manager (SPM)" - depends on ARCH_QCOM || COMPILE_TEST - select QCOM_SCM + depends on QCOM_SCM + default ARCH_QCOM if ARM help Enable the support for the Qualcomm Subsystem Power Manager, used to manage cores, L2 low power modes and to configure the internal @@ -238,9 +236,10 @@ config QCOM_SPM config QCOM_STATS tristate "Qualcomm Sleep stats driver" - depends on (ARCH_QCOM && DEBUG_FS) || COMPILE_TEST + depends on DEBUG_FS || COMPILE_TEST depends on QCOM_SMEM depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n + default m if ARCH_QCOM help Qualcomm Technologies, Inc. (QTI) Sleep stats driver to read the shared memory exported by the remote processor related to @@ -249,18 +248,18 @@ config QCOM_STATS config QCOM_WCNSS_CTRL tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM || COMPILE_TEST depends on RPMSG + default m if ARCH_QCOM help Client driver for the WCNSS_CTRL SMD channel, used to download nv firmware to a newly booted WCNSS chip. config QCOM_APR tristate "Qualcomm APR/GPR Bus (Asynchronous/Generic Packet Router)" - depends on ARCH_QCOM || COMPILE_TEST depends on RPMSG depends on NET select QCOM_PDR_HELPERS + default m if ARCH_QCOM help Enable APR IPC protocol support between application processor and QDSP6. APR is @@ -269,9 +268,10 @@ config QCOM_APR config QCOM_ICC_BWMON tristate "Qualcomm Interconnect Bandwidth Monitor driver" - depends on ARCH_QCOM || COMPILE_TEST + depends on ARM64 || COMPILE_TEST select PM_OPP select REGMAP_MMIO + default m if ARCH_QCOM help Sets up driver monitoring bandwidth on various interconnects and based on that voting for interconnect bandwidth, adjusting their @@ -282,20 +282,42 @@ config QCOM_ICC_BWMON the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. -config QCOM_INLINE_CRYPTO_ENGINE - tristate - select QCOM_SCM - config QCOM_PBS tristate "PBS trigger support for Qualcomm PMICs" depends on SPMI + default m if ARCH_QCOM help This driver supports configuring software programmable boot sequencer (PBS) trigger event through PBS RAM on Qualcomm Technologies, Inc. PMICs. This module provides the APIs to the client drivers that wants to send the PBS trigger event to the PBS RAM. -endmenu +endif + +# Options selected by other drivers from different subsystems must be outside +# of the menuconfig if-block: + +config QCOM_INLINE_CRYPTO_ENGINE + tristate + select QCOM_SCM + +config QCOM_KRYO_L2_ACCESSORS + bool + depends on ARM64 + +config QCOM_MDT_LOADER + tristate + select QCOM_SCM + +config QCOM_PDR_HELPERS + tristate + select QCOM_QMI_HELPERS + select QCOM_PDR_MSG + depends on NET + +config QCOM_QMI_HELPERS + tristate + depends on NET config QCOM_UBWC_CONFIG tristate diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 8948b5fd42d2..22c8099cf6bb 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -2305,6 +2305,20 @@ static const struct llcc_slice_config sdm845_data[] = {{ }, }; +static const struct llcc_slice_config shikra_data[] = { + { + .usecase_id = LLCC_ECC, + .slice_id = 26, + .max_cap = 256, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0x3, + .cache_mode = 0, + .activate_on_init = true, + .vict_prio = true, + }, +}; + static const struct llcc_slice_config sm6350_data[] = { { .usecase_id = LLCC_CPUSS, @@ -4575,6 +4589,15 @@ static const struct qcom_llcc_config sdm845_cfg[] = { }, }; +static const struct qcom_llcc_config shikra_cfg[] = { + { + .sct_data = shikra_data, + .size = ARRAY_SIZE(shikra_data), + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config sm6350_cfg[] = { { .sct_data = sm6350_data, @@ -4752,6 +4775,11 @@ static const struct qcom_sct_config sdm845_cfgs = { .num_config = ARRAY_SIZE(sdm845_cfg), }; +static const struct qcom_sct_config shikra_cfgs = { + .llcc_config = shikra_cfg, + .num_config = ARRAY_SIZE(shikra_cfg), +}; + static const struct qcom_sct_config sm6350_cfgs = { .llcc_config = sm6350_cfg, .num_config = ARRAY_SIZE(sm6350_cfg), @@ -5632,6 +5660,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs }, { .compatible = "qcom,sdm670-llcc", .data = &sdm670_cfgs }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs }, + { .compatible = "qcom,shikra-llcc", .data = &shikra_cfgs }, { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs }, { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs }, diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index c004d444d698..137992456b71 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -13,7 +13,7 @@ #include <linux/firmware.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/firmware/qcom/qcom_scm.h> +#include <linux/firmware/qcom/qcom_pas.h> #include <linux/sizes.h> #include <linux/slab.h> #include <linux/soc/qcom/mdt_loader.h> @@ -229,7 +229,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_context *ctx) + struct qcom_pas_context *ctx) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -271,7 +271,7 @@ static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, goto out; } - ret = qcom_scm_pas_init_image(pas_id, metadata, metadata_len, ctx); + ret = qcom_pas_init_image(pas_id, metadata, metadata_len, ctx); kfree(metadata); if (ret) { /* Invalid firmware metadata */ @@ -280,7 +280,7 @@ static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, } if (relocate) { - ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); + ret = qcom_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); if (ret) { /* Unable to set up relocation */ dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); @@ -472,7 +472,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * firmware segments (e.g., .bXX files). Authentication of the segments done * by a separate call. * - * The PAS context must be initialized using qcom_scm_pas_context_init() + * The PAS context must be initialized using devm_qcom_pas_context_alloc() * prior to invoking this function. * * @ctx: Pointer to the PAS (Peripheral Authentication Service) context @@ -483,7 +483,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * * Return: 0 on success or a negative error code on failure. */ -int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw, +int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base) { int ret; diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c index 0dc1a7946050..64ca99d7fad9 100644 --- a/drivers/soc/qcom/qcom_pd_mapper.c +++ b/drivers/soc/qcom/qcom_pd_mapper.c @@ -310,6 +310,24 @@ static const struct qcom_pdm_domain_data cdsp_root_pd = { .services = { NULL }, }; +static const struct qcom_pdm_domain_data cdsp1_root_pd = { + .domain = "msm/cdsp1/root_pd", + .instance_id = 125, + .services = { NULL }, +}; + +static const struct qcom_pdm_domain_data gpdsp_root_pd = { + .domain = "msm/gpdsp/root_pd", + .instance_id = 192, + .services = { NULL }, +}; + +static const struct qcom_pdm_domain_data gpdsp1_root_pd = { + .domain = "msm/gpdsp1/root_pd", + .instance_id = 241, + .services = { NULL }, +}; + static const struct qcom_pdm_domain_data slpi_root_pd = { .domain = "msm/slpi/root_pd", .instance_id = 90, @@ -425,6 +443,24 @@ static const struct qcom_pdm_domain_data *qcs615_domains[] = { NULL, }; +static const struct qcom_pdm_domain_data *qcs8300_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &cdsp_root_pd, + &gpdsp_root_pd, + NULL, +}; + +static const struct qcom_pdm_domain_data *sa8775p_domains[] = { + &adsp_audio_pd, + &adsp_root_pd, + &cdsp_root_pd, + &cdsp1_root_pd, + &gpdsp_root_pd, + &gpdsp1_root_pd, + NULL, +}; + static const struct qcom_pdm_domain_data *sc7180_domains[] = { &adsp_audio_pd, &adsp_root_pd_pdr, @@ -602,6 +638,8 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = { { .compatible = "qcom,qcm6490", .data = sc7280_domains, }, { .compatible = "qcom,qcs404", .data = qcs404_domains, }, { .compatible = "qcom,qcs615", .data = qcs615_domains, }, + { .compatible = "qcom,qcs8300", .data = qcs8300_domains, }, + { .compatible = "qcom,sa8775p", .data = sa8775p_domains, }, { .compatible = "qcom,sc7180", .data = sc7180_domains, }, { .compatible = "qcom,sc7280", .data = sc7280_domains, }, { .compatible = "qcom,sc8180x", .data = sc8180x_domains, }, diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 2e380faf9080..e7122444f12a 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -54,6 +54,8 @@ static const struct subsystem_data subsystems[] = { { "cdsp1", 607, 12 }, { "gpdsp0", 607, 17 }, { "gpdsp1", 607, 18 }, + { "soccp", 607, 19 }, + { "dcp", 607, 22 }, { "slpi", 608, 3 }, { "gpu", 609, 0 }, { "display", 610, 0 }, diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index c6f7d5c9c493..66928ca40b9a 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -944,17 +944,30 @@ static int rpmh_rsc_pd_callback(struct notifier_block *nfb, return NOTIFY_OK; } +static void rpmh_rsc_pd_detach(void *data) +{ + dev_pm_genpd_remove_notifier(data); +} + static int rpmh_rsc_pd_attach(struct rsc_drv *drv, struct device *dev) { int ret; - pm_runtime_enable(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + drv->genpd_nb.notifier_call = rpmh_rsc_pd_callback; ret = dev_pm_genpd_add_notifier(dev, &drv->genpd_nb); if (ret) - pm_runtime_disable(dev); + return ret; - return ret; + return devm_add_action_or_reset(dev, rpmh_rsc_pd_detach, dev); +} + +static void rpmh_rsc_cpu_pm_unregister(void *data) +{ + cpu_pm_unregister_notifier(data); } static int rpmh_probe_tcs_config(struct platform_device *pdev, struct rsc_drv *drv) @@ -1107,7 +1120,15 @@ static int rpmh_rsc_probe(struct platform_device *pdev) return ret; } else { drv->rsc_pm.notifier_call = rpmh_rsc_cpu_pm_callback; - cpu_pm_register_notifier(&drv->rsc_pm); + ret = cpu_pm_register_notifier(&drv->rsc_pm); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&pdev->dev, + rpmh_rsc_cpu_pm_unregister, + &drv->rsc_pm); + if (ret) + return ret; } } @@ -1122,13 +1143,7 @@ static int rpmh_rsc_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, drv); drv->dev = &pdev->dev; - ret = devm_of_platform_populate(&pdev->dev); - if (ret && pdev->dev.pm_domain) { - dev_pm_genpd_remove_notifier(&pdev->dev); - pm_runtime_disable(&pdev->dev); - } - - return ret; + return devm_of_platform_populate(&pdev->dev); } static const struct of_device_id rpmh_drv_match[] = { diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index a3cb6d61bb65..0209a02c390f 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -145,6 +145,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,sdm660", .data = &ubwc_1_0_hbb14 }, { .compatible = "qcom,sdm670", .data = &ubwc_2_0_hbb14, }, { .compatible = "qcom,sdm845", .data = &ubwc_2_0_hbb15, }, + { .compatible = "qcom,shikra", .data = &ubwc_0_0_hbb15, }, { .compatible = "qcom,sm4250", .data = &ubwc_1_0_hbb14, }, { .compatible = "qcom,sm6115", .data = &ubwc_1_0_hbb14, }, { .compatible = "qcom,sm6125", .data = &ubwc_1_0_hbb14, }, |