diff options
Diffstat (limited to 'drivers/gpu/drm/panel')
| -rw-r--r-- | drivers/gpu/drm/panel/Kconfig | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/Makefile | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c | 140 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-ilitek-ili9806e.c | 402 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-lincolntech-lcd197.c | 262 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-raydium-rm692e5.c | 238 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-sitronix-st7703.c | 836 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c | 433 |
8 files changed, 1451 insertions, 882 deletions
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index bf4eadfe21cb..9f49b0189d3b 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -205,6 +205,15 @@ config DRM_PANEL_ILITEK_ILI9805 Say Y if you want to enable support for panels based on the Ilitek ILI9805 controller. +config DRM_PANEL_ILITEK_ILI9806E + tristate "Ilitek ILI9806E-based panels" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y if you want to enable support for panels based on the + Ilitek ILI9806E controller. + config DRM_PANEL_ILITEK_ILI9881C tristate "Ilitek ILI9881C-based panels" depends on OF @@ -328,6 +337,17 @@ config DRM_PANEL_LEADTEK_LTK500HD1829 24 bit RGB per pixel. It provides a MIPI DSI interface to the host and has a built-in LED backlight. +config DRM_PANEL_LINCOLNTECH_LCD197 + tristate "Lincoln Technologies lcd197 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for lincolntech lcd197 + TFT-LCD modules. The panel has a 1080x1920 resolution and uses + 24 bit RGB per pixel. It provides a MIPI DSI interface to + the host. + config DRM_PANEL_LG_LB035Q02 tristate "LG LB035Q024573 RGB panel" depends on GPIOLIB && OF && SPI diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 051b75b3df7b..5581387707c6 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9805) += panel-ilitek-ili9805.o +obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9806E) += panel-ilitek-ili9806e.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9882T) += panel-ilitek-ili9882t.o obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o @@ -33,6 +34,7 @@ obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o +obj-$(CONFIG_DRM_PANEL_LINCOLNTECH_LCD197) += panel-lincolntech-lcd197.o obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o diff --git a/drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c b/drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c index bcaa63d1955f..b05a663c134c 100644 --- a/drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c +++ b/drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c @@ -33,119 +33,97 @@ static void tm5p5_nt35596_reset(struct tm5p5_nt35596 *ctx) usleep_range(15000, 16000); } -static int tm5p5_nt35596_on(struct tm5p5_nt35596 *ctx) +static void tm5p5_nt35596_on(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = ctx->dsi; - - mipi_dsi_generic_write_seq(dsi, 0xff, 0x05); - mipi_dsi_generic_write_seq(dsi, 0xfb, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xc5, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xff, 0x04); - mipi_dsi_generic_write_seq(dsi, 0x01, 0x84); - mipi_dsi_generic_write_seq(dsi, 0x05, 0x25); - mipi_dsi_generic_write_seq(dsi, 0x06, 0x01); - mipi_dsi_generic_write_seq(dsi, 0x07, 0x20); - mipi_dsi_generic_write_seq(dsi, 0x08, 0x06); - mipi_dsi_generic_write_seq(dsi, 0x09, 0x08); - mipi_dsi_generic_write_seq(dsi, 0x0a, 0x10); - mipi_dsi_generic_write_seq(dsi, 0x0b, 0x10); - mipi_dsi_generic_write_seq(dsi, 0x0c, 0x10); - mipi_dsi_generic_write_seq(dsi, 0x0d, 0x14); - mipi_dsi_generic_write_seq(dsi, 0x0e, 0x14); - mipi_dsi_generic_write_seq(dsi, 0x0f, 0x14); - mipi_dsi_generic_write_seq(dsi, 0x10, 0x14); - mipi_dsi_generic_write_seq(dsi, 0x11, 0x14); - mipi_dsi_generic_write_seq(dsi, 0x12, 0x14); - mipi_dsi_generic_write_seq(dsi, 0x17, 0xf3); - mipi_dsi_generic_write_seq(dsi, 0x18, 0xc0); - mipi_dsi_generic_write_seq(dsi, 0x19, 0xc0); - mipi_dsi_generic_write_seq(dsi, 0x1a, 0xc0); - mipi_dsi_generic_write_seq(dsi, 0x1b, 0xb3); - mipi_dsi_generic_write_seq(dsi, 0x1c, 0xb3); - mipi_dsi_generic_write_seq(dsi, 0x1d, 0xb3); - mipi_dsi_generic_write_seq(dsi, 0x1e, 0xb3); - mipi_dsi_generic_write_seq(dsi, 0x1f, 0xb3); - mipi_dsi_generic_write_seq(dsi, 0x20, 0xb3); - mipi_dsi_generic_write_seq(dsi, 0xfb, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xff, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xfb, 0x01); - mipi_dsi_generic_write_seq(dsi, 0x35, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xd3, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xd4, 0x04); - mipi_dsi_generic_write_seq(dsi, 0x5e, 0x0d); - mipi_dsi_generic_write_seq(dsi, 0x11, 0x00); - msleep(100); - mipi_dsi_generic_write_seq(dsi, 0x29, 0x00); - mipi_dsi_generic_write_seq(dsi, 0x53, 0x24); - - return 0; + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x05); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc5, 0x31); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x04); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x01, 0x84); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x05, 0x25); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x06, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x07, 0x20); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x08, 0x06); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x09, 0x08); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0a, 0x10); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0b, 0x10); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0c, 0x10); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0d, 0x14); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0e, 0x14); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0f, 0x14); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x10, 0x14); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x11, 0x14); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x12, 0x14); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x17, 0xf3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x18, 0xc0); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x19, 0xc0); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1a, 0xc0); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1b, 0xb3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1c, 0xb3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1d, 0xb3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1e, 0xb3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1f, 0xb3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x20, 0xb3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x35, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd3, 0x06); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd4, 0x04); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x5e, 0x0d); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x11, 0x00); + + mipi_dsi_msleep(dsi_ctx, 100); + + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x29, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x53, 0x24); } -static int tm5p5_nt35596_off(struct tm5p5_nt35596 *ctx) +static void tm5p5_nt35596_off(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; - - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(60); + mipi_dsi_dcs_set_display_off_multi(dsi_ctx); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } + mipi_dsi_msleep(dsi_ctx, 60); - mipi_dsi_dcs_write_seq(dsi, 0x4f, 0x01); + mipi_dsi_dcs_enter_sleep_mode_multi(dsi_ctx); - return 0; + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x4f, 0x01); } static int tm5p5_nt35596_prepare(struct drm_panel *panel) { struct tm5p5_nt35596 *ctx = to_tm5p5_nt35596(panel); - struct device *dev = &ctx->dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = ctx->dsi}; - ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) { - dev_err(dev, "Failed to enable regulators: %d\n", ret); - return ret; - } + dsi_ctx.accum_err = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (dsi_ctx.accum_err) + return dsi_ctx.accum_err; tm5p5_nt35596_reset(ctx); - ret = tm5p5_nt35596_on(ctx); - if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); + tm5p5_nt35596_on(&dsi_ctx); + + if (dsi_ctx.accum_err) { gpiod_set_value_cansleep(ctx->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - return ret; } - return 0; + return dsi_ctx.accum_err; } static int tm5p5_nt35596_unprepare(struct drm_panel *panel) { struct tm5p5_nt35596 *ctx = to_tm5p5_nt35596(panel); - struct device *dev = &ctx->dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = ctx->dsi}; - ret = tm5p5_nt35596_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + tm5p5_nt35596_off(&dsi_ctx); gpiod_set_value_cansleep(ctx->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - return 0; + return dsi_ctx.accum_err; } static const struct drm_display_mode tm5p5_nt35596_mode = { diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c new file mode 100644 index 000000000000..e4a44cd26c4d --- /dev/null +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/gpio/consumer.h> +#include <linux/kernel.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> + +#include <video/mipi_display.h> + +struct panel_desc { + const struct drm_display_mode *display_mode; + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + unsigned int lanes; + void (*init_sequence)(struct mipi_dsi_multi_context *ctx); +}; + +struct ili9806e_panel { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[2]; + const struct panel_desc *desc; + enum drm_panel_orientation orientation; +}; + +static const char * const regulator_names[] = { + "vdd", + "vccio", +}; + +static inline struct ili9806e_panel *to_ili9806e_panel(struct drm_panel *panel) +{ + return container_of(panel, struct ili9806e_panel, panel); +} + +static int ili9806e_power_on(struct ili9806e_panel *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + int ret; + + gpiod_set_value(ctx->reset_gpio, 1); + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) { + dev_err(&dsi->dev, "regulator bulk enable failed: %d\n", ret); + return ret; + } + + usleep_range(10000, 20000); + gpiod_set_value(ctx->reset_gpio, 0); + usleep_range(10000, 20000); + + return 0; +} + +static int ili9806e_power_off(struct ili9806e_panel *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + int ret; + + gpiod_set_value(ctx->reset_gpio, 1); + + ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret) + dev_err(&dsi->dev, "regulator bulk disable failed: %d\n", ret); + + return ret; +} + +static int ili9806e_on(struct ili9806e_panel *ili9806e) +{ + struct mipi_dsi_multi_context ctx = { .dsi = ili9806e->dsi }; + + if (ili9806e->desc->init_sequence) + ili9806e->desc->init_sequence(&ctx); + + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 120); + mipi_dsi_dcs_set_display_on_multi(&ctx); + + return ctx.accum_err; +} + +static int ili9806e_off(struct ili9806e_panel *panel) +{ + struct mipi_dsi_multi_context ctx = { .dsi = panel->dsi }; + + mipi_dsi_dcs_set_display_off_multi(&ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 120); + + return ctx.accum_err; +} + +static int ili9806e_prepare(struct drm_panel *panel) +{ + struct ili9806e_panel *ctx = to_ili9806e_panel(panel); + int ret; + + ret = ili9806e_power_on(ctx); + if (ret < 0) + return ret; + + ret = ili9806e_on(ctx); + if (ret < 0) { + ili9806e_power_off(ctx); + return ret; + } + + return 0; +} + +static int ili9806e_unprepare(struct drm_panel *panel) +{ + struct ili9806e_panel *ctx = to_ili9806e_panel(panel); + struct mipi_dsi_device *dsi = ctx->dsi; + int ret; + + ili9806e_off(ctx); + + ret = ili9806e_power_off(ctx); + if (ret < 0) + dev_err(&dsi->dev, "power off failed: %d\n", ret); + + return ret; +} + +static int ili9806e_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct ili9806e_panel *ctx = to_ili9806e_panel(panel); + const struct drm_display_mode *mode = ctx->desc->display_mode; + + return drm_connector_helper_get_modes_fixed(connector, mode); +} + +static enum drm_panel_orientation ili9806e_get_orientation(struct drm_panel *panel) +{ + struct ili9806e_panel *ctx = to_ili9806e_panel(panel); + + return ctx->orientation; +} + +static const struct drm_panel_funcs ili9806e_funcs = { + .prepare = ili9806e_prepare, + .unprepare = ili9806e_unprepare, + .get_modes = ili9806e_get_modes, + .get_orientation = ili9806e_get_orientation, +}; + +static int ili9806e_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct ili9806e_panel *ctx; + int i, ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->desc = device_get_match_data(dev); + + for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) + ctx->supplies[i].supply = regulator_names[i]; + + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) + return ret; + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + mipi_dsi_set_drvdata(dsi, ctx); + ctx->dsi = dsi; + + dsi->mode_flags = ctx->desc->mode_flags; + dsi->format = ctx->desc->format; + dsi->lanes = ctx->desc->lanes; + + drm_panel_init(&ctx->panel, dev, &ili9806e_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation); + if (ret) + return dev_err_probe(dev, ret, "Failed to get orientation\n"); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + ctx->panel.prepare_prev_first = true; + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void ili9806e_dsi_remove(struct mipi_dsi_device *dsi) +{ + struct ili9806e_panel *ctx = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&ctx->panel); +} + +static void com35h3p70ulc_init(struct mipi_dsi_multi_context *ctx) +{ + /* Switch to page 1 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01); + /* Interface Settings */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x18); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01); + /* Panel Settings */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x0d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x09); + /* Power Control */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x30); + mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44); + mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x89); + mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x8e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0xd9); + mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x33); + mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x33); + mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x90); + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x90); + mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00); + /* Gamma Settings */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0d); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x0b); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x15); + mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x12); + mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x28); + mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0d); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x0b); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x21); + mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x17); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x0a); + + /* Switch to page 7 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07); + /* Power Control */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x32); + + /* Switch to page 6 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06); + /* GIP settings */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x02); + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x02); + mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x88); + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0x55); + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x50); + mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x43); + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x0b); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x45); + mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45); + mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x02); + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0x88); + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xaa); + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xbb); + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x66); + mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x12); + + /* Switch to page 0 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00); + /* Interface Pixel format */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x60); +}; + +static const struct drm_display_mode com35h3p70ulc_default_mode = { + .clock = 22400, + .hdisplay = 480, + .hsync_start = 480 + 16, + .hsync_end = 480 + 16 + 16, + .htotal = 480 + 16 + 16 + 16, + .vdisplay = 640, + .vsync_start = 640 + 52, + .vsync_end = 640 + 52 + 4, + .vtotal = 640 + 52 + 4 + 16, + .width_mm = 53, + .height_mm = 71, +}; + +static const struct panel_desc com35h3p70ulc_desc = { + .init_sequence = com35h3p70ulc_init, + .display_mode = &com35h3p70ulc_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 2, +}; + +static const struct of_device_id ili9806e_of_match[] = { + { .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc }, + { } +}; +MODULE_DEVICE_TABLE(of, ili9806e_of_match); + +static struct mipi_dsi_driver ili9806e_dsi_driver = { + .driver = { + .name = "ili9806e-dsi", + .of_match_table = ili9806e_of_match, + }, + .probe = ili9806e_dsi_probe, + .remove = ili9806e_dsi_remove, +}; +module_mipi_dsi_driver(ili9806e_dsi_driver); + +MODULE_AUTHOR("Gunnar Dibbern <gunnar.dibbern@lht.dlh.de>"); +MODULE_AUTHOR("Michael Walle <mwalle@kernel.org>"); +MODULE_DESCRIPTION("Ilitek ILI9806E Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-lincolntech-lcd197.c b/drivers/gpu/drm/panel/panel-lincolntech-lcd197.c new file mode 100644 index 000000000000..032c542aab0f --- /dev/null +++ b/drivers/gpu/drm/panel/panel-lincolntech-lcd197.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 BayLibre, SAS + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/drm_device.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> + +struct lincoln_lcd197_panel { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct regulator *supply; + struct gpio_desc *enable_gpio; + struct gpio_desc *reset_gpio; +}; + +static inline +struct lincoln_lcd197_panel *to_lincoln_lcd197_panel(struct drm_panel *panel) +{ + return container_of(panel, struct lincoln_lcd197_panel, panel); +} + +static int lincoln_lcd197_panel_prepare(struct drm_panel *panel) +{ + struct lincoln_lcd197_panel *lcd = to_lincoln_lcd197_panel(panel); + struct mipi_dsi_multi_context ctx = { .dsi = lcd->dsi }; + int err; + + gpiod_set_value_cansleep(lcd->enable_gpio, 0); + err = regulator_enable(lcd->supply); + if (err < 0) + return err; + + gpiod_set_value_cansleep(lcd->enable_gpio, 1); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(lcd->reset_gpio, 1); + usleep_range(5000, 6000); + gpiod_set_value_cansleep(lcd->reset_gpio, 0); + msleep(50); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0xff, 0x83, 0x99); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd2, 0x55); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x02, 0x04, 0x70, 0x90, 0x01, + 0x32, 0x33, 0x11, 0x11, 0x4d, 0x57, 0x56, 0x73, + 0x02, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x00, 0x80, 0x80, 0xae, 0x0a, + 0x0e, 0x75, 0x11, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x00, 0xff, 0x04, 0xa4, 0x02, + 0xa0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x02, 0x00, + 0x24, 0x02, 0x04, 0x0a, 0x21, 0x03, 0x00, 0x00, + 0x08, 0xa6, 0x88, 0x04, 0xa4, 0x02, 0xa0, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x02, 0x00, 0x24, 0x02, + 0x04, 0x0a, 0x00, 0x00, 0x08, 0xa6, 0x00, 0x08, + 0x11); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x18, 0x32, 0x10, 0x09, 0x00, 0x09, + 0x32, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x11, 0x00, 0x02, 0x02, 0x03, 0x00, + 0x00, 0x00, 0x0a, 0x40); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd5, 0x18, 0x18, 0x18, 0x18, 0x21, + 0x20, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19, 0x18, + 0x18, 0x18, 0x18, 0x03, 0x02, 0x01, 0x00, 0x2f, + 0x2f, 0x30, 0x30, 0x31, 0x31, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd6, 0x18, 0x18, 0x18, 0x18, 0x20, + 0x21, 0x19, 0x19, 0x18, 0x18, 0x19, 0x19, 0x18, + 0x18, 0x18, 0x18, 0x00, 0x01, 0x02, 0x03, 0x2f, + 0x2f, 0x30, 0x30, 0x31, 0x31, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0x0a, 0xbe, 0xfa, 0xa0, 0x0a, + 0xbe, 0xfa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0x0f, 0xff, 0xff, 0xe0, 0x0f, + 0xff, 0xff, 0xe0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0x0f, 0xff, 0xff, 0xe0, 0x0f, + 0xff, 0xff, 0xe0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xe0, 0x01, 0x11, 0x1c, 0x17, 0x39, + 0x43, 0x54, 0x51, 0x5a, 0x64, 0x6c, 0x74, 0x7a, + 0x83, 0x8d, 0x92, 0x99, 0xa4, 0xa9, 0xb4, 0xaa, + 0xba, 0xbe, 0x63, 0x5e, 0x69, 0x73, 0x01, 0x11, + 0x1c, 0x17, 0x39, 0x43, 0x54, 0x51, 0x5a, 0x64, + 0x6c, 0x74, 0x7a, 0x83, 0x8d, 0x92, 0x99, 0xa4, + 0xa7, 0xb2, 0xa9, 0xba, 0xbe, 0x63, 0x5e, 0x69, + 0x73); + mipi_dsi_usleep_range(&ctx, 200, 300); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb6, 0x92, 0x92); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xcc, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xbf, 0x40, 0x41, 0x50, 0x49); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xc6, 0xff, 0xf9); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x25, 0x5a); + mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x02); + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 120); + + if (ctx.accum_err) { + gpiod_set_value_cansleep(lcd->enable_gpio, 0); + gpiod_set_value_cansleep(lcd->reset_gpio, 1); + regulator_disable(lcd->supply); + } + + return ctx.accum_err; +} + +static int lincoln_lcd197_panel_unprepare(struct drm_panel *panel) +{ + struct lincoln_lcd197_panel *lcd = to_lincoln_lcd197_panel(panel); + struct mipi_dsi_multi_context ctx = { .dsi = lcd->dsi }; + + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); + mipi_dsi_usleep_range(&ctx, 5000, 6000); + gpiod_set_value_cansleep(lcd->enable_gpio, 0); + gpiod_set_value_cansleep(lcd->reset_gpio, 1); + regulator_disable(lcd->supply); + + return ctx.accum_err; +} + +static int lincoln_lcd197_panel_enable(struct drm_panel *panel) +{ + struct lincoln_lcd197_panel *lcd = to_lincoln_lcd197_panel(panel); + struct mipi_dsi_multi_context ctx = { .dsi = lcd->dsi }; + + mipi_dsi_dcs_set_display_on_multi(&ctx); + mipi_dsi_msleep(&ctx, 20); + + return ctx.accum_err; +} + +static int lincoln_lcd197_panel_disable(struct drm_panel *panel) +{ + struct lincoln_lcd197_panel *lcd = to_lincoln_lcd197_panel(panel); + struct mipi_dsi_multi_context ctx = { .dsi = lcd->dsi }; + + mipi_dsi_dcs_set_display_off_multi(&ctx); + mipi_dsi_msleep(&ctx, 50); + + return ctx.accum_err; +} + +static const struct drm_display_mode lcd197_mode = { + .clock = 154002, + .hdisplay = 1080, + .hsync_start = 1080 + 20, + .hsync_end = 1080 + 20 + 6, + .htotal = 1080 + 204, + .vdisplay = 1920, + .vsync_start = 1920 + 4, + .vsync_end = 1920 + 4 + 4, + .vtotal = 1920 + 79, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + .width_mm = 79, + .height_mm = 125, + .type = DRM_MODE_TYPE_DRIVER, +}; + +static int lincoln_lcd197_panel_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + return drm_connector_helper_get_modes_fixed(connector, &lcd197_mode); +} + +static const struct drm_panel_funcs lincoln_lcd197_panel_funcs = { + .prepare = lincoln_lcd197_panel_prepare, + .unprepare = lincoln_lcd197_panel_unprepare, + .enable = lincoln_lcd197_panel_enable, + .disable = lincoln_lcd197_panel_disable, + .get_modes = lincoln_lcd197_panel_get_modes, +}; + +static int lincoln_lcd197_panel_probe(struct mipi_dsi_device *dsi) +{ + struct lincoln_lcd197_panel *lcd; + struct device *dev = &dsi->dev; + int err; + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST); + + lcd = devm_kzalloc(&dsi->dev, sizeof(*lcd), GFP_KERNEL); + if (!lcd) + return -ENOMEM; + + mipi_dsi_set_drvdata(dsi, lcd); + lcd->dsi = dsi; + + lcd->supply = devm_regulator_get(dev, "power"); + if (IS_ERR(lcd->supply)) + return dev_err_probe(dev, PTR_ERR(lcd->supply), + "failed to get power supply"); + + lcd->enable_gpio = devm_gpiod_get(dev, "enable", + GPIOD_OUT_HIGH); + if (IS_ERR(lcd->enable_gpio)) + return dev_err_probe(dev, PTR_ERR(lcd->enable_gpio), + "failed to get enable gpio"); + + lcd->reset_gpio = devm_gpiod_get(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(lcd->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(lcd->reset_gpio), + "failed to get reset gpio"); + + drm_panel_init(&lcd->panel, dev, + &lincoln_lcd197_panel_funcs, DRM_MODE_CONNECTOR_DSI); + + err = drm_panel_of_backlight(&lcd->panel); + if (err) + return err; + + drm_panel_add(&lcd->panel); + err = mipi_dsi_attach(dsi); + if (err) + drm_panel_remove(&lcd->panel); + + return err; +} + +static void lincoln_lcd197_panel_remove(struct mipi_dsi_device *dsi) +{ + struct lincoln_lcd197_panel *lcd = mipi_dsi_get_drvdata(dsi); + int err; + + err = mipi_dsi_detach(dsi); + if (err < 0) + dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); + + drm_panel_remove(&lcd->panel); +} + +static const struct of_device_id lincoln_lcd197_of_match[] = { + { .compatible = "lincolntech,lcd197", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, lincoln_lcd197_of_match); + +static struct mipi_dsi_driver lincoln_lcd197_panel_driver = { + .driver = { + .name = "panel-lincolntech-lcd197", + .of_match_table = lincoln_lcd197_of_match, + }, + .probe = lincoln_lcd197_panel_probe, + .remove = lincoln_lcd197_panel_remove, +}; +module_mipi_dsi_driver(lincoln_lcd197_panel_driver); + +MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); +MODULE_DESCRIPTION("Lincoln Technologies LCD197 panel driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-raydium-rm692e5.c b/drivers/gpu/drm/panel/panel-raydium-rm692e5.c index 21d97f6b8a2f..ea1b728e85a2 100644 --- a/drivers/gpu/drm/panel/panel-raydium-rm692e5.c +++ b/drivers/gpu/drm/panel/panel-raydium-rm692e5.c @@ -40,176 +40,136 @@ static void rm692e5_reset(struct rm692e5_panel *ctx) usleep_range(10000, 11000); } -static int rm692e5_on(struct rm692e5_panel *ctx) +static void rm692e5_on(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; - - dsi->mode_flags |= MIPI_DSI_MODE_LPM; - - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x41); - mipi_dsi_generic_write_seq(dsi, 0xd6, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x16); - mipi_dsi_generic_write_seq(dsi, 0x8a, 0x87); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x71); - mipi_dsi_generic_write_seq(dsi, 0x82, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xc6, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc7, 0x2c); - mipi_dsi_generic_write_seq(dsi, 0xc8, 0x64); - mipi_dsi_generic_write_seq(dsi, 0xc9, 0x3c); - mipi_dsi_generic_write_seq(dsi, 0xca, 0x80); - mipi_dsi_generic_write_seq(dsi, 0xcb, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xcc, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x38); - mipi_dsi_generic_write_seq(dsi, 0x18, 0x13); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0xf4); - mipi_dsi_generic_write_seq(dsi, 0x00, 0xff); - mipi_dsi_generic_write_seq(dsi, 0x01, 0xff); - mipi_dsi_generic_write_seq(dsi, 0x02, 0xcf); - mipi_dsi_generic_write_seq(dsi, 0x03, 0xbc); - mipi_dsi_generic_write_seq(dsi, 0x04, 0xb9); - mipi_dsi_generic_write_seq(dsi, 0x05, 0x99); - mipi_dsi_generic_write_seq(dsi, 0x06, 0x02); - mipi_dsi_generic_write_seq(dsi, 0x07, 0x0a); - mipi_dsi_generic_write_seq(dsi, 0x08, 0xe0); - mipi_dsi_generic_write_seq(dsi, 0x09, 0x4c); - mipi_dsi_generic_write_seq(dsi, 0x0a, 0xeb); - mipi_dsi_generic_write_seq(dsi, 0x0b, 0xe8); - mipi_dsi_generic_write_seq(dsi, 0x0c, 0x32); - mipi_dsi_generic_write_seq(dsi, 0x0d, 0x07); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0xf4); - mipi_dsi_generic_write_seq(dsi, 0x0d, 0xc0); - mipi_dsi_generic_write_seq(dsi, 0x0e, 0xff); - mipi_dsi_generic_write_seq(dsi, 0x0f, 0xff); - mipi_dsi_generic_write_seq(dsi, 0x10, 0x33); - mipi_dsi_generic_write_seq(dsi, 0x11, 0x6f); - mipi_dsi_generic_write_seq(dsi, 0x12, 0x6e); - mipi_dsi_generic_write_seq(dsi, 0x13, 0xa6); - mipi_dsi_generic_write_seq(dsi, 0x14, 0x80); - mipi_dsi_generic_write_seq(dsi, 0x15, 0x02); - mipi_dsi_generic_write_seq(dsi, 0x16, 0x38); - mipi_dsi_generic_write_seq(dsi, 0x17, 0xd3); - mipi_dsi_generic_write_seq(dsi, 0x18, 0x3a); - mipi_dsi_generic_write_seq(dsi, 0x19, 0xba); - mipi_dsi_generic_write_seq(dsi, 0x1a, 0xcc); - mipi_dsi_generic_write_seq(dsi, 0x1b, 0x01); - - ret = mipi_dsi_dcs_nop(dsi); - if (ret < 0) { - dev_err(dev, "Failed to nop: %d\n", ret); - return ret; - } - msleep(32); - - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x38); - mipi_dsi_generic_write_seq(dsi, 0x18, 0x13); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0xd1); - mipi_dsi_generic_write_seq(dsi, 0xd3, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd0, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd2, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd4, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb4, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0xf9); - mipi_dsi_generic_write_seq(dsi, 0x00, 0xaf); - mipi_dsi_generic_write_seq(dsi, 0x1d, 0x37); - mipi_dsi_generic_write_seq(dsi, 0x44, 0x0a, 0x7b); - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xfa, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xc2, 0x08); - mipi_dsi_generic_write_seq(dsi, 0x35, 0x00); - mipi_dsi_generic_write_seq(dsi, 0x51, 0x05, 0x42); - - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(100); - - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } - - return 0; + dsi_ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x41); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd6, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x16); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8a, 0x87); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x71); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x82, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc6, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc7, 0x2c); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc8, 0x64); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc9, 0x3c); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xca, 0x80); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xcb, 0x02); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xcc, 0x02); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x38); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x18, 0x13); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0xf4); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x00, 0xff); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x01, 0xff); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x02, 0xcf); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x03, 0xbc); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x04, 0xb9); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x05, 0x99); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x06, 0x02); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x07, 0x0a); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x08, 0xe0); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x09, 0x4c); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0a, 0xeb); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0b, 0xe8); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0c, 0x32); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0d, 0x07); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0xf4); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0d, 0xc0); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0e, 0xff); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0f, 0xff); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x10, 0x33); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x11, 0x6f); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x12, 0x6e); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x13, 0xa6); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x14, 0x80); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x15, 0x02); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x16, 0x38); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x17, 0xd3); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x18, 0x3a); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x19, 0xba); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1a, 0xcc); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1b, 0x01); + + mipi_dsi_dcs_nop_multi(dsi_ctx); + + mipi_dsi_msleep(dsi_ctx, 32); + + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x38); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x18, 0x13); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0xd1); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd3, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd0, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd2, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd4, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xb4, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0xf9); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x00, 0xaf); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1d, 0x37); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x44, 0x0a, 0x7b); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfa, 0x01); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc2, 0x08); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x35, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x51, 0x05, 0x42); + + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 100); + mipi_dsi_dcs_set_display_on_multi(dsi_ctx); } static int rm692e5_disable(struct drm_panel *panel) { struct rm692e5_panel *ctx = to_rm692e5_panel(panel); struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - mipi_dsi_generic_write_seq(dsi, 0xfe, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0x00); - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(100); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); - return 0; + mipi_dsi_msleep(&dsi_ctx, 100); + + return dsi_ctx.accum_err; } static int rm692e5_prepare(struct drm_panel *panel) { struct rm692e5_panel *ctx = to_rm692e5_panel(panel); struct drm_dsc_picture_parameter_set pps; - struct device *dev = &ctx->dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; - ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) { - dev_err(dev, "Failed to enable regulators: %d\n", ret); - return ret; - } + dsi_ctx.accum_err = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (dsi_ctx.accum_err) + return dsi_ctx.accum_err; rm692e5_reset(ctx); - ret = rm692e5_on(ctx); - if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); - gpiod_set_value_cansleep(ctx->reset_gpio, 1); - regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - return ret; - } + rm692e5_on(&dsi_ctx); drm_dsc_pps_payload_pack(&pps, &ctx->dsc); - ret = mipi_dsi_picture_parameter_set(ctx->dsi, &pps); - if (ret < 0) { - dev_err(panel->dev, "failed to transmit PPS: %d\n", ret); - return ret; - } - - ret = mipi_dsi_compression_mode(ctx->dsi, true); - if (ret < 0) { - dev_err(dev, "failed to enable compression mode: %d\n", ret); - return ret; - } + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps); + mipi_dsi_compression_mode_ext_multi(&dsi_ctx, true, MIPI_DSI_COMPRESSION_DSC, 0); + mipi_dsi_msleep(&dsi_ctx, 28); - msleep(28); - - mipi_dsi_generic_write_seq(ctx->dsi, 0xfe, 0x40); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0x40); /* 0x05 -> 90Hz, 0x00 -> 60Hz */ - mipi_dsi_generic_write_seq(ctx->dsi, 0xbd, 0x05); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x05); - mipi_dsi_generic_write_seq(ctx->dsi, 0xfe, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0x00); - return 0; + if (dsi_ctx.accum_err) { + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + } + + return dsi_ctx.accum_err; } static int rm692e5_unprepare(struct drm_panel *panel) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c index 77b30e045a57..67e8e45498cb 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c @@ -69,7 +69,7 @@ struct st7703_panel_desc { unsigned int lanes; unsigned long mode_flags; enum mipi_dsi_pixel_format format; - int (*init_sequence)(struct st7703 *ctx); + void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx); }; static inline struct st7703 *panel_to_st7703(struct drm_panel *panel) @@ -77,62 +77,58 @@ static inline struct st7703 *panel_to_st7703(struct drm_panel *panel) return container_of(panel, struct st7703, panel); } -static int jh057n_init_sequence(struct st7703 *ctx) +static void jh057n_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - /* * Init sequence was supplied by the panel vendor. Most of the commands * resemble the ST7703 but the number of parameters often don't match * so it's likely a clone. */ - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC, - 0xF1, 0x12, 0x83); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF, - 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00, - 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR, - 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, - 0x00); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEQ, - 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00, - 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETBGP, 0x08, 0x08); - msleep(20); - - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1, - 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12, - 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, - 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, - 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, - 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP2, - 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, - 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, - 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A, - 0xA5, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGAMMA, - 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37, - 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11, - 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, - 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, - 0x11, 0x18); - msleep(20); - - return 0; + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, + 0xF1, 0x12, 0x83); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, + 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00, + 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, + 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, + 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, + 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00, + 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x08, 0x08); + mipi_dsi_msleep(dsi_ctx, 20); + + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, + 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12, + 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, + 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, + 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, + 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, + 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A, + 0xA5, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, + 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37, + 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11, + 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, + 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, + 0x11, 0x18); + mipi_dsi_msleep(dsi_ctx, 20); } static const struct drm_display_mode jh057n00900_mode = { @@ -159,163 +155,159 @@ static const struct st7703_panel_desc jh057n00900_panel_desc = { .init_sequence = jh057n_init_sequence, }; -static int xbd599_init_sequence(struct st7703 *ctx) +static void xbd599_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - /* * Init sequence was supplied by the panel vendor. */ /* Magic sequence to unlock user commands below. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, - 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */ - 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */ - 0x05, /* IHSRX = x6 (Low High Speed driving ability) */ - 0xF9, /* TX_CLK_SEL = fDSICLK/16 */ - 0x0E, /* HFP_OSC (min. HFP number in DSI mode) */ - 0x0E, /* HBP_OSC (min. HBP number in DSI mode) */ - /* The rest is undocumented in ST7703 datasheet */ - 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, - 0x4F, 0x11, 0x00, 0x00, 0x37); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, - 0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */ - 0x22, /* DT = 15ms XDK_ECP = x2 */ - 0x20, /* PFM_DC_DIV = /1 */ - 0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, + 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */ + 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */ + 0x05, /* IHSRX = x6 (Low High Speed driving ability) */ + 0xF9, /* TX_CLK_SEL = fDSICLK/16 */ + 0x0E, /* HFP_OSC (min. HFP number in DSI mode) */ + 0x0E, /* HBP_OSC (min. HBP number in DSI mode) */ + /* The rest is undocumented in ST7703 datasheet */ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, + 0x4F, 0x11, 0x00, 0x00, 0x37); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, + 0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */ + 0x22, /* DT = 15ms XDK_ECP = x2 */ + 0x20, /* PFM_DC_DIV = /1 */ + 0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */); /* RGB I/F porch timing */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, - 0x10, /* VBP_RGB_GEN */ - 0x10, /* VFP_RGB_GEN */ - 0x05, /* DE_BP_RGB_GEN */ - 0x05, /* DE_FP_RGB_GEN */ - /* The rest is undocumented in ST7703 datasheet */ - 0x03, 0xFF, - 0x00, 0x00, - 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, + 0x10, /* VBP_RGB_GEN */ + 0x10, /* VFP_RGB_GEN */ + 0x05, /* DE_BP_RGB_GEN */ + 0x05, /* DE_FP_RGB_GEN */ + /* The rest is undocumented in ST7703 datasheet */ + 0x03, 0xFF, + 0x00, 0x00, + 0x00, 0x00); /* Source driving settings. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, - 0x73, /* N_POPON */ - 0x73, /* N_NOPON */ - 0x50, /* I_POPON */ - 0x50, /* I_NOPON */ - 0x00, /* SCR[31,24] */ - 0xC0, /* SCR[23,16] */ - 0x08, /* SCR[15,8] */ - 0x70, /* SCR[7,0] */ - 0x00 /* Undocumented */); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, + 0x73, /* N_POPON */ + 0x73, /* N_NOPON */ + 0x50, /* I_POPON */ + 0x50, /* I_NOPON */ + 0x00, /* SCR[31,24] */ + 0xC0, /* SCR[23,16] */ + 0x08, /* SCR[15,8] */ + 0x70, /* SCR[7,0] */ + 0x00 /* Undocumented */); /* NVDDD_SEL = -1.8V, VDDD_SEL = out of range (possibly 1.9V?) */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); /* * SS_PANEL = 1 (reverse scan), GS_PANEL = 0 (normal scan) * REV_PANEL = 1 (normally black panel), BGR_PANEL = 1 (BGR) */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); /* Zig-Zag Type C column inversion. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); /* Set display resolution. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, - 0xF0, /* NL = 240 */ - 0x12, /* RES_V_LSB = 0, BLK_CON = VSSD, - * RESO_SEL = 720RGB - */ - 0xF0 /* WHITE_GND_EN = 1 (GND), - * WHITE_FRAME_SEL = 7 frames, - * ISC = 0 frames - */); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, - 0x00, /* PNOEQ */ - 0x00, /* NNOEQ */ - 0x0B, /* PEQGND */ - 0x0B, /* NEQGND */ - 0x10, /* PEQVCI */ - 0x10, /* NEQVCI */ - 0x00, /* PEQVCI1 */ - 0x00, /* NEQVCI1 */ - 0x00, /* reserved */ - 0x00, /* reserved */ - 0xFF, /* reserved */ - 0x00, /* reserved */ - 0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */ - 0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in) - * VEDIO_NO_CHECK_EN = 0 - * ESD_WHITE_GND_EN = 0 - * ESD_DET_TIME_SEL = 0 frames - */); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, - 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */ - 0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */ - 0x32, /* VRP */ - 0x32, /* VRN */ - 0x77, /* reserved */ - 0xF1, /* APS = 1 (small), - * VGL_DET_EN = 1, VGH_DET_EN = 1, - * VGL_TURBO = 1, VGH_TURBO = 1 - */ - 0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */ - 0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */ - 0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */ - 0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */ - 0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */ - 0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, + 0xF0, /* NL = 240 */ + 0x12, /* RES_V_LSB = 0, BLK_CON = VSSD, + * RESO_SEL = 720RGB + */ + 0xF0 /* WHITE_GND_EN = 1 (GND), + * WHITE_FRAME_SEL = 7 frames, + * ISC = 0 frames + */); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, + 0x00, /* PNOEQ */ + 0x00, /* NNOEQ */ + 0x0B, /* PEQGND */ + 0x0B, /* NEQGND */ + 0x10, /* PEQVCI */ + 0x10, /* NEQVCI */ + 0x00, /* PEQVCI1 */ + 0x00, /* NEQVCI1 */ + 0x00, /* reserved */ + 0x00, /* reserved */ + 0xFF, /* reserved */ + 0x00, /* reserved */ + 0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */ + 0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in) + * VEDIO_NO_CHECK_EN = 0 + * ESD_WHITE_GND_EN = 0 + * ESD_DET_TIME_SEL = 0 frames + */); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, + 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */ + 0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */ + 0x32, /* VRP */ + 0x32, /* VRN */ + 0x77, /* reserved */ + 0xF1, /* APS = 1 (small), + * VGL_DET_EN = 1, VGH_DET_EN = 1, + * VGL_TURBO = 1, VGH_TURBO = 1 + */ + 0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */ + 0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */ + 0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */ + 0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */ + 0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */ + 0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */); /* Reference voltage. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, - 0x07, /* VREF_SEL = 4.2V */ - 0x07 /* NVREF_SEL = 4.2V */); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, + 0x07, /* VREF_SEL = 4.2V */ + 0x07 /* NVREF_SEL = 4.2V */); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, - 0x2C, /* VCOMDC_F = -0.67V */ - 0x2C /* VCOMDC_B = -0.67V */); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, + 0x2C, /* VCOMDC_F = -0.67V */ + 0x2C /* VCOMDC_B = -0.67V */); /* Undocumented command. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); /* This command is to set forward GIP timing. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, - 0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12, - 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, - 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, - 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, - 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, + 0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12, + 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, + 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, + 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); /* This command is to set backward GIP timing. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, - 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, - 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, - 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A, - 0xA5, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, + 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, + 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A, + 0xA5, 0x00, 0x00, 0x00, 0x00); /* Adjust the gamma characteristics of the panel. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, - 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35, - 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12, - 0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, - 0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, - 0x12, 0x18); - - return 0; + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, + 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35, + 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12, + 0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, + 0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, + 0x12, 0x18); } static const struct drm_display_mode xbd599_mode = { @@ -341,72 +333,68 @@ static const struct st7703_panel_desc xbd599_desc = { .init_sequence = xbd599_init_sequence, }; -static int rg353v2_init_sequence(struct st7703 *ctx) +static void rg353v2_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - /* * Init sequence was supplied by the panel vendor. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, - 0xda, 0x80); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, - 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x92, 0x92); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, - 0xf0, 0x63); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, - 0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, - 0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, - 0x00, 0x00, 0x12, 0x50, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32, - 0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33, - 0x33); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, - 0x00, 0xff); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, - 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, - 0x02); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d, - 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d, - 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07, - 0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, - 0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, - 0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, - 0xc0, 0x10); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00, - 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80, - 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, - 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, - 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, - 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, - 0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42, - 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, - 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); - - return 0; + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, + 0xda, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, + 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x0a, 0x0a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x92, 0x92); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, + 0xf0, 0x63); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, + 0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, + 0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x47); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, + 0x00, 0x00, 0x12, 0x50, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32, + 0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33, + 0x33); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, + 0x00, 0xff); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, + 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, + 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d, + 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d, + 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07, + 0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, + 0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, + 0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, + 0xc0, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00, + 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80, + 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, + 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, + 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, + 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, + 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); } static const struct drm_display_mode rg353v2_mode = { @@ -433,68 +421,64 @@ static const struct st7703_panel_desc rg353v2_desc = { .init_sequence = rg353v2_init_sequence, }; -static int rgb30panel_init_sequence(struct st7703 *ctx) +static void rgb30panel_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - /* Init sequence extracted from Powkiddy RGB30 BSP kernel. */ /* * For some reason this specific panel must be taken out of sleep * before the full init sequence, or else it will not display. */ - mipi_dsi_dcs_exit_sleep_mode(dsi); - msleep(250); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, - 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, - 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, - 0x63); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, - 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, - 0x00, 0x00, 0x12, 0x70, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x46); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, - 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, - 0xc0, 0x10); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32, - 0x32, 0x77, 0xf1, 0xcc, 0xcc, 0x77, 0x77, 0x33, - 0x33); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x88, 0x88); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10, - 0x0f, 0xa1, 0x80, 0x12, 0x31, 0x23, 0x47, 0x86, - 0xa1, 0x80, 0x47, 0x08, 0x00, 0x00, 0x0d, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, - 0x48, 0x02, 0x8b, 0xaf, 0x46, 0x02, 0x88, 0x88, - 0x88, 0x88, 0x88, 0x48, 0x13, 0x8b, 0xaf, 0x57, - 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01, - 0x01, 0x78, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x4f, 0x31, 0x8b, 0xa8, 0x31, 0x75, 0x88, 0x88, - 0x88, 0x88, 0x88, 0x4f, 0x20, 0x8b, 0xa8, 0x20, - 0x64, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, - 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0xa1, 0x80, 0x00, 0x00, 0x00, - 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f, - 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 0x10, - 0x13, 0x15, 0x14, 0x15, 0x10, 0x17, 0x00, 0x0a, - 0x0f, 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, - 0x10, 0x13, 0x15, 0x14, 0x15, 0x10, 0x17); - - return 0; + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 250); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, + 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, + 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, + 0x63); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, + 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, + 0x00, 0x00, 0x12, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x46); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, + 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, + 0xc0, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32, + 0x32, 0x77, 0xf1, 0xcc, 0xcc, 0x77, 0x77, 0x33, + 0x33); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x0a, 0x0a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x88, 0x88); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10, + 0x0f, 0xa1, 0x80, 0x12, 0x31, 0x23, 0x47, 0x86, + 0xa1, 0x80, 0x47, 0x08, 0x00, 0x00, 0x0d, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, + 0x48, 0x02, 0x8b, 0xaf, 0x46, 0x02, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x48, 0x13, 0x8b, 0xaf, 0x57, + 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01, + 0x01, 0x78, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x4f, 0x31, 0x8b, 0xa8, 0x31, 0x75, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x4f, 0x20, 0x8b, 0xa8, 0x20, + 0x64, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, + 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0xa1, 0x80, 0x00, 0x00, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f, + 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 0x10, + 0x13, 0x15, 0x14, 0x15, 0x10, 0x17, 0x00, 0x0a, + 0x0f, 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, + 0x10, 0x13, 0x15, 0x14, 0x15, 0x10, 0x17); } static const struct drm_display_mode rgb30panel_mode = { @@ -521,70 +505,66 @@ static const struct st7703_panel_desc rgb30panel_desc = { .init_sequence = rgb30panel_init_sequence, }; -static int rgb10max3_panel_init_sequence(struct st7703 *ctx) +static void rgb10max3_panel_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - /* Init sequence extracted from Powkiddy RGB10MAX3 BSP kernel. */ - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 0xda, - 0x80); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0xc8, 0x02, 0x30); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, - 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x04, 0x04); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x78, 0x78); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, - 0x63); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, - 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, - 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, - 0x00, 0x00, 0x12, 0x70, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x25, 0x00, 0x32, - 0x32, 0x77, 0xe1, 0xff, 0xff, 0xcc, 0xcc, 0x77, - 0x77); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, - 0x00, 0xff); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, - 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, - 0x02); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x04, 0x07, - 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 0x0e, - 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17, 0x00, 0x04, - 0x07, 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, - 0x0e, 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x03, 0x03, 0x03, 0x03, - 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0xff, 0x80, - 0xc0, 0x10); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x08, 0x00, - 0x00, 0x41, 0xf8, 0x12, 0x31, 0x23, 0x37, 0x86, - 0x11, 0xc8, 0x37, 0x2a, 0x00, 0x00, 0x0c, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x88, 0x20, 0x46, 0x02, 0x88, 0x88, 0x88, 0x88, - 0x88, 0x88, 0xff, 0x88, 0x31, 0x57, 0x13, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x00, 0x1a, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x8f, 0x13, 0x31, 0x75, 0x88, 0x88, 0x88, 0x88, - 0x88, 0x88, 0xf8, 0x8f, 0x02, 0x20, 0x64, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0xf8, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); - - return 0; + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 0xda, + 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xc8, 0x02, 0x30); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, + 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x04, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x78, 0x78); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, + 0x63); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, + 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, + 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x47); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, + 0x00, 0x00, 0x12, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x25, 0x00, 0x32, + 0x32, 0x77, 0xe1, 0xff, 0xff, 0xcc, 0xcc, 0x77, + 0x77); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, + 0x00, 0xff); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, + 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, + 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x04, 0x07, + 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 0x0e, + 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17, 0x00, 0x04, + 0x07, 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, + 0x0e, 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x03, 0x03, 0x03, 0x03, + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0xff, 0x80, + 0xc0, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x08, 0x00, + 0x00, 0x41, 0xf8, 0x12, 0x31, 0x23, 0x37, 0x86, + 0x11, 0xc8, 0x37, 0x2a, 0x00, 0x00, 0x0c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x88, 0x20, 0x46, 0x02, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0xff, 0x88, 0x31, 0x57, 0x13, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x00, 0x1a, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x8f, 0x13, 0x31, 0x75, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0xf8, 0x8f, 0x02, 0x20, 0x64, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); } static const struct drm_display_mode rgb10max3_panel_mode = { @@ -611,66 +591,62 @@ static const struct st7703_panel_desc rgb10max3_panel_desc = { .init_sequence = rgb10max3_panel_init_sequence, }; -static int gameforcechi_init_sequence(struct st7703 *ctx) +static void gameforcechi_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - /* * Init sequence was supplied by the panel vendor. Panel will not * respond to commands until it is brought out of sleep mode first. */ - mipi_dsi_dcs_exit_sleep_mode(dsi); - msleep(250); - - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x31, 0x81, 0x05, 0xf9, - 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, - 0x00, 0x02, 0x4f, 0xd1, 0x00, 0x00, 0x37); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x0c, 0x10, 0x0a, - 0x50, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, - 0x00, 0x00, 0x08, 0x70, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x46); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0xf0); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, - 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, - 0xc0, 0x10); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0x00, 0x1e, - 0x1e, 0x77, 0xe1, 0xcc, 0xdd, 0x67, 0x77, 0x33, - 0x33); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x10, 0x10); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x6c, 0x7c); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0x08, 0x00, 0x0e, 0x00, - 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x10, - 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, - 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, - 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, - 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, - 0x13, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, - 0x88, 0x88, 0x88, 0x81, 0x88, 0xba, 0x06, 0x42, - 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x10, - 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00); - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0b, - 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0x0a, 0x0b, - 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18, 0x00, 0x07, - 0x0b, 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0xa0, - 0x0b, 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18); - - return 0; + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 250); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x31, 0x81, 0x05, 0xf9, + 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, + 0x00, 0x02, 0x4f, 0xd1, 0x00, 0x00, 0x37); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x0c, 0x10, 0x0a, + 0x50, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, + 0x00, 0x00, 0x08, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x46); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x00, 0x13, 0xf0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, + 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, + 0xc0, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x53, 0x00, 0x1e, + 0x1e, 0x77, 0xe1, 0xcc, 0xdd, 0x67, 0x77, 0x33, + 0x33); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x10, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x6c, 0x7c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0x08, 0x00, 0x0e, 0x00, + 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x10, + 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, + 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, + 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, + 0x13, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x81, 0x88, 0xba, 0x06, 0x42, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x10, + 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0b, + 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0x0a, 0x0b, + 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18, 0x00, 0x07, + 0x0b, 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0xa0, + 0x0b, 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18); } static const struct drm_display_mode gameforcechi_mode = { @@ -701,50 +677,37 @@ static int st7703_enable(struct drm_panel *panel) { struct st7703 *ctx = panel_to_st7703(panel); struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; - ret = ctx->desc->init_sequence(ctx); - if (ret < 0) { - dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret); - return ret; - } + ctx->desc->init_sequence(&dsi_ctx); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); /* It takes the controller 120 msec to wake up after sleep. */ - msleep(120); + mipi_dsi_msleep(&dsi_ctx, 120); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret) - return ret; + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - dev_dbg(ctx->dev, "Panel init sequence done\n"); + if (!dsi_ctx.accum_err) + dev_dbg(ctx->dev, "Panel init sequence done\n"); - return 0; + return dsi_ctx.accum_err; } static int st7703_disable(struct drm_panel *panel) { struct st7703 *ctx = panel_to_st7703(panel); struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - dev_err(ctx->dev, "Failed to turn off the display: %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); /* It takes the controller 120 msec to enter sleep mode. */ - msleep(120); + mipi_dsi_msleep(&dsi_ctx, 120); - return 0; + return dsi_ctx.accum_err; } static int st7703_unprepare(struct drm_panel *panel) @@ -840,10 +803,11 @@ static int allpixelson_set(void *data, u64 val) { struct st7703 *ctx = data; struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; dev_dbg(ctx->dev, "Setting all pixels on\n"); - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_ALL_PIXEL_ON); - msleep(val * 1000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, ST7703_CMD_ALL_PIXEL_ON); + mipi_dsi_msleep(&dsi_ctx, val * 1000); /* * Reset the panel to get video back. NOTE: This isn't a @@ -856,7 +820,7 @@ static int allpixelson_set(void *data, u64 val) drm_panel_prepare(&ctx->panel); drm_panel_enable(&ctx->panel); - return 0; + return dsi_ctx.accum_err; } DEFINE_SIMPLE_ATTRIBUTE(allpixelson_fops, NULL, diff --git a/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c b/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c index 6d44970dccd9..f2198fa29735 100644 --- a/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c +++ b/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c @@ -44,248 +44,229 @@ static void truly_nt35521_reset(struct truly_nt35521 *ctx) static int truly_nt35521_on(struct truly_nt35521 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xff, 0xaa, 0x55, 0xa5, 0x80); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x11, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xf7, 0x20, 0x00); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xb1, 0x21); - mipi_dsi_generic_write_seq(dsi, 0xbd, 0x01, 0xa0, 0x10, 0x08, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xb8, 0x01, 0x02, 0x0c, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xbb, 0x11, 0x11); - mipi_dsi_generic_write_seq(dsi, 0xbc, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb6, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x09, 0x09); - mipi_dsi_generic_write_seq(dsi, 0xb1, 0x09, 0x09); - mipi_dsi_generic_write_seq(dsi, 0xbc, 0x8c, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xbd, 0x8c, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xca, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc0, 0x04); - mipi_dsi_generic_write_seq(dsi, 0xbe, 0xb5); - mipi_dsi_generic_write_seq(dsi, 0xb3, 0x35, 0x35); - mipi_dsi_generic_write_seq(dsi, 0xb4, 0x25, 0x25); - mipi_dsi_generic_write_seq(dsi, 0xb9, 0x43, 0x43); - mipi_dsi_generic_write_seq(dsi, 0xba, 0x24, 0x24); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xee, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xb0, - 0x00, 0xb2, 0x00, 0xb3, 0x00, 0xb6, 0x00, 0xc3, - 0x00, 0xce, 0x00, 0xe1, 0x00, 0xf3, 0x01, 0x11); - mipi_dsi_generic_write_seq(dsi, 0xb1, - 0x01, 0x2e, 0x01, 0x5c, 0x01, 0x82, 0x01, 0xc3, - 0x01, 0xfe, 0x02, 0x00, 0x02, 0x37, 0x02, 0x77); - mipi_dsi_generic_write_seq(dsi, 0xb2, - 0x02, 0xa1, 0x02, 0xd7, 0x02, 0xfe, 0x03, 0x2c, - 0x03, 0x4b, 0x03, 0x63, 0x03, 0x8f, 0x03, 0x90); - mipi_dsi_generic_write_seq(dsi, 0xb3, 0x03, 0x96, 0x03, 0x98); - mipi_dsi_generic_write_seq(dsi, 0xb4, - 0x00, 0x81, 0x00, 0x8b, 0x00, 0x9c, 0x00, 0xa9, - 0x00, 0xb5, 0x00, 0xcb, 0x00, 0xdf, 0x01, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xb5, - 0x01, 0x1f, 0x01, 0x51, 0x01, 0x7a, 0x01, 0xbf, - 0x01, 0xfa, 0x01, 0xfc, 0x02, 0x34, 0x02, 0x76); - mipi_dsi_generic_write_seq(dsi, 0xb6, - 0x02, 0x9f, 0x02, 0xd7, 0x02, 0xfc, 0x03, 0x2c, - 0x03, 0x4a, 0x03, 0x63, 0x03, 0x8f, 0x03, 0xa2); - mipi_dsi_generic_write_seq(dsi, 0xb7, 0x03, 0xb8, 0x03, 0xba); - mipi_dsi_generic_write_seq(dsi, 0xb8, - 0x00, 0x01, 0x00, 0x02, 0x00, 0x0e, 0x00, 0x2a, - 0x00, 0x41, 0x00, 0x67, 0x00, 0x87, 0x00, 0xb9); - mipi_dsi_generic_write_seq(dsi, 0xb9, - 0x00, 0xe2, 0x01, 0x22, 0x01, 0x54, 0x01, 0xa3, - 0x01, 0xe6, 0x01, 0xe7, 0x02, 0x24, 0x02, 0x67); - mipi_dsi_generic_write_seq(dsi, 0xba, - 0x02, 0x93, 0x02, 0xcd, 0x02, 0xf6, 0x03, 0x31, - 0x03, 0x6c, 0x03, 0xe9, 0x03, 0xef, 0x03, 0xf4); - mipi_dsi_generic_write_seq(dsi, 0xbb, 0x03, 0xf6, 0x03, 0xf7); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x22, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb1, 0x22, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb2, 0x05, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb3, 0x05, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb4, 0x05, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb5, 0x05, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xba, 0x53, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xbb, 0x53, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xbc, 0x53, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xbd, 0x53, 0x00, 0x60, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc0, 0x00, 0x34, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc1, 0x00, 0x00, 0x34, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc2, 0x00, 0x00, 0x34, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc3, 0x00, 0x00, 0x34, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc4, 0x60); - mipi_dsi_generic_write_seq(dsi, 0xc5, 0xc0); - mipi_dsi_generic_write_seq(dsi, 0xc6, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc7, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x05); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb1, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb2, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb3, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb4, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb5, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb6, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb7, 0x17, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb8, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb9, 0x00, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xba, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xbb, 0x02, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xbc, 0x02, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xbd, 0x03, 0x03, 0x00, 0x03, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xc0, 0x0b); - mipi_dsi_generic_write_seq(dsi, 0xc1, 0x09); - mipi_dsi_generic_write_seq(dsi, 0xc2, 0xa6); - mipi_dsi_generic_write_seq(dsi, 0xc3, 0x05); - mipi_dsi_generic_write_seq(dsi, 0xc4, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc5, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xc6, 0x22); - mipi_dsi_generic_write_seq(dsi, 0xc7, 0x03); - mipi_dsi_generic_write_seq(dsi, 0xc8, 0x07, 0x20); - mipi_dsi_generic_write_seq(dsi, 0xc9, 0x03, 0x20); - mipi_dsi_generic_write_seq(dsi, 0xca, 0x01, 0x60); - mipi_dsi_generic_write_seq(dsi, 0xcb, 0x01, 0x60); - mipi_dsi_generic_write_seq(dsi, 0xcc, 0x00, 0x00, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xcd, 0x00, 0x00, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xce, 0x00, 0x00, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xcf, 0x00, 0x00, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xd1, 0x00, 0x05, 0x01, 0x07, 0x10); - mipi_dsi_generic_write_seq(dsi, 0xd2, 0x10, 0x05, 0x05, 0x03, 0x10); - mipi_dsi_generic_write_seq(dsi, 0xd3, 0x20, 0x00, 0x43, 0x07, 0x10); - mipi_dsi_generic_write_seq(dsi, 0xd4, 0x30, 0x00, 0x43, 0x07, 0x10); - mipi_dsi_generic_write_seq(dsi, 0xd0, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd5, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd6, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd7, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xe5, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xe6, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xe7, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xe8, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xe9, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xea, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xeb, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xec, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xed, 0x30); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x06); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xb1, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xb2, 0x2d, 0x2e); - mipi_dsi_generic_write_seq(dsi, 0xb3, 0x31, 0x34); - mipi_dsi_generic_write_seq(dsi, 0xb4, 0x29, 0x2a); - mipi_dsi_generic_write_seq(dsi, 0xb5, 0x12, 0x10); - mipi_dsi_generic_write_seq(dsi, 0xb6, 0x18, 0x16); - mipi_dsi_generic_write_seq(dsi, 0xb7, 0x00, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xb8, 0x08, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xb9, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xba, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xbb, 0x31, 0x08); - mipi_dsi_generic_write_seq(dsi, 0xbc, 0x03, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xbd, 0x17, 0x19); - mipi_dsi_generic_write_seq(dsi, 0xbe, 0x11, 0x13); - mipi_dsi_generic_write_seq(dsi, 0xbf, 0x2a, 0x29); - mipi_dsi_generic_write_seq(dsi, 0xc0, 0x34, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xc1, 0x2e, 0x2d); - mipi_dsi_generic_write_seq(dsi, 0xc2, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xc3, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xc4, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xc5, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xc6, 0x2e, 0x2d); - mipi_dsi_generic_write_seq(dsi, 0xc7, 0x31, 0x34); - mipi_dsi_generic_write_seq(dsi, 0xc8, 0x29, 0x2a); - mipi_dsi_generic_write_seq(dsi, 0xc9, 0x17, 0x19); - mipi_dsi_generic_write_seq(dsi, 0xca, 0x11, 0x13); - mipi_dsi_generic_write_seq(dsi, 0xcb, 0x03, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xcc, 0x08, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xcd, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xce, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xcf, 0x31, 0x08); - mipi_dsi_generic_write_seq(dsi, 0xd0, 0x00, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xd1, 0x12, 0x10); - mipi_dsi_generic_write_seq(dsi, 0xd2, 0x18, 0x16); - mipi_dsi_generic_write_seq(dsi, 0xd3, 0x2a, 0x29); - mipi_dsi_generic_write_seq(dsi, 0xd4, 0x34, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xd5, 0x2d, 0x2e); - mipi_dsi_generic_write_seq(dsi, 0xd6, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xd7, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xe5, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xe6, 0x31, 0x31); - mipi_dsi_generic_write_seq(dsi, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd9, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xe7, 0x00); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x02); - mipi_dsi_generic_write_seq(dsi, 0xf7, 0x47); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x0a); - mipi_dsi_generic_write_seq(dsi, 0xf7, 0x02); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x17); - mipi_dsi_generic_write_seq(dsi, 0xf4, 0x60); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xf9, 0x46); - mipi_dsi_generic_write_seq(dsi, 0x6f, 0x11); - mipi_dsi_generic_write_seq(dsi, 0xf3, 0x01); - mipi_dsi_generic_write_seq(dsi, 0x35, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd9, 0x02, 0x03, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xb1, 0x6c, 0x21); - mipi_dsi_generic_write_seq(dsi, 0xf0, 0x55, 0xaa, 0x52, 0x00, 0x00); - mipi_dsi_generic_write_seq(dsi, 0x35, 0x00); - - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x11, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x20, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x21); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x01, 0xa0, 0x10, 0x08, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x01, 0x02, 0x0c, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x11, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x09, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x09, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x8c, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x8c, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x04); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0xb5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x35, 0x35); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x25, 0x25); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x43, 0x43); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x24, 0x24); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, + 0x00, 0xb2, 0x00, 0xb3, 0x00, 0xb6, 0x00, 0xc3, + 0x00, 0xce, 0x00, 0xe1, 0x00, 0xf3, 0x01, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, + 0x01, 0x2e, 0x01, 0x5c, 0x01, 0x82, 0x01, 0xc3, + 0x01, 0xfe, 0x02, 0x00, 0x02, 0x37, 0x02, 0x77); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, + 0x02, 0xa1, 0x02, 0xd7, 0x02, 0xfe, 0x03, 0x2c, + 0x03, 0x4b, 0x03, 0x63, 0x03, 0x8f, 0x03, 0x90); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x03, 0x96, 0x03, 0x98); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, + 0x00, 0x81, 0x00, 0x8b, 0x00, 0x9c, 0x00, 0xa9, + 0x00, 0xb5, 0x00, 0xcb, 0x00, 0xdf, 0x01, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, + 0x01, 0x1f, 0x01, 0x51, 0x01, 0x7a, 0x01, 0xbf, + 0x01, 0xfa, 0x01, 0xfc, 0x02, 0x34, 0x02, 0x76); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, + 0x02, 0x9f, 0x02, 0xd7, 0x02, 0xfc, 0x03, 0x2c, + 0x03, 0x4a, 0x03, 0x63, 0x03, 0x8f, 0x03, 0xa2); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x03, 0xb8, 0x03, 0xba); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x0e, 0x00, 0x2a, + 0x00, 0x41, 0x00, 0x67, 0x00, 0x87, 0x00, 0xb9); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, + 0x00, 0xe2, 0x01, 0x22, 0x01, 0x54, 0x01, 0xa3, + 0x01, 0xe6, 0x01, 0xe7, 0x02, 0x24, 0x02, 0x67); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, + 0x02, 0x93, 0x02, 0xcd, 0x02, 0xf6, 0x03, 0x31, + 0x03, 0x6c, 0x03, 0xe9, 0x03, 0xef, 0x03, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x03, 0xf6, 0x03, 0xf7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x22, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x22, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x05, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x05, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x05, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x05, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x53, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x53, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x53, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x53, 0x00, 0x60, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x00, 0x34, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x00, 0x00, 0x34, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x00, 0x00, 0x34, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x00, 0x00, 0x34, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0xc0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x05); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x17, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x00, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x02, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x02, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x03, 0x03, 0x00, 0x03, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x0b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0xa6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x05); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x03); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x07, 0x20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x03, 0x20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x01, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x01, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x00, 0x00, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x00, 0x00, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x00, 0x00, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x00, 0x00, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x00, 0x05, 0x01, 0x07, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x10, 0x05, 0x05, 0x03, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x20, 0x00, 0x43, 0x07, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x30, 0x00, 0x43, 0x07, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x2d, 0x2e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x31, 0x34); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x29, 0x2a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x12, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x18, 0x16); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x00, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x08, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x31, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x03, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x17, 0x19); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0x11, 0x13); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x2a, 0x29); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x34, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x2e, 0x2d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x2e, 0x2d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x31, 0x34); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x29, 0x2a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x17, 0x19); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x11, 0x13); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x03, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x08, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x31, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x00, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x12, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x18, 0x16); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x2a, 0x29); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x34, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x2d, 0x2e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x31, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x47); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x02); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x17); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0x46); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x02, 0x03, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x6c, 0x21); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x00, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } usleep_range(1000, 2000); - mipi_dsi_generic_write_seq(dsi, 0x53, 0x24); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x53, 0x24); - return 0; + return dsi_ctx.accum_err; } static int truly_nt35521_off(struct truly_nt35521 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(50); - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(150); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 50); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 150); - return 0; + return dsi_ctx.accum_err; } static int truly_nt35521_prepare(struct drm_panel *panel) |