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path: root/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/umc_v12_0.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/umc_v12_0.h28
1 files changed, 0 insertions, 28 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
index 63b7e7254526..9d9e84d8d3bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
@@ -26,31 +26,6 @@
#include "soc15_common.h"
#include "amdgpu.h"
-#define UMC_V12_0_NODE_DIST 0x40000000
-#define UMC_V12_0_INST_DIST 0x40000
-
-/* UMC register per channel offset */
-#define UMC_V12_0_PER_CHANNEL_OFFSET 0x400
-
-/* UMC cross node offset */
-#define UMC_V12_0_CROSS_NODE_OFFSET 0x100000000
-
-/* OdEccErrCnt max value */
-#define UMC_V12_0_CE_CNT_MAX 0xffff
-/* umc ce interrupt threshold */
-#define UMC_V12_0_CE_INT_THRESHOLD 0xffff
-/* umc ce count initial value */
-#define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD)
-
-/* number of umc channel instance with memory map register access */
-#define UMC_V12_0_CHANNEL_INSTANCE_NUM 8
-/* number of umc instance with memory map register access */
-#define UMC_V12_0_UMC_INSTANCE_NUM 4
-
-/* Total channel instances for all available umc nodes */
-#define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) \
- (UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
-
/* one piece of normalized address is mapped to 8 pieces of physical address */
#define UMC_V12_0_NA_MAP_PA_NUM 8
/* R13 bit shift should be considered, double the number */
@@ -75,9 +50,6 @@
/* row bits in MCA address */
#define UMC_V12_0_MA_R0_BIT 10
-#define MCA_UMC_HWID_V12_0 0x96
-#define MCA_UMC_MCATYPE_V12_0 0x0
-
#define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \
(((_ipid_lo) >> 12) & 0xF))
#define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7)