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path: root/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c73
1 files changed, 6 insertions, 67 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 3fde9be74690..05cce4bde73e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -298,7 +298,8 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
case CHIP_STONEY:
chip_name = "stoney";
break;
- default: BUG();
+ default:
+ return -EINVAL;
}
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -810,7 +811,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
u32 tmp;
u64 gpu_addr;
- r = amdgpu_device_wb_get(adev, &index);
+ r = amdgpu_wb_get(adev, &index);
if (r)
return r;
@@ -841,7 +842,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
r = -ETIMEDOUT;
error_free_wb:
- amdgpu_device_wb_free(adev, index);
+ amdgpu_wb_free(adev, index);
return r;
}
@@ -864,7 +865,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
u64 gpu_addr;
long r;
- r = amdgpu_device_wb_get(adev, &index);
+ r = amdgpu_wb_get(adev, &index);
if (r)
return r;
@@ -908,7 +909,7 @@ err1:
amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
- amdgpu_device_wb_free(adev, index);
+ amdgpu_wb_free(adev, index);
return r;
}
@@ -1237,65 +1238,6 @@ static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- struct amdgpu_device *adev = ip_block->adev;
- u32 srbm_soft_reset = 0;
- u32 tmp = RREG32(mmSRBM_STATUS2);
-
- if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
- (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
- srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
- srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
- }
-
- if (srbm_soft_reset) {
- adev->sdma.srbm_soft_reset = srbm_soft_reset;
- return true;
- } else {
- adev->sdma.srbm_soft_reset = 0;
- return false;
- }
-}
-
-static int sdma_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- struct amdgpu_device *adev = ip_block->adev;
- u32 srbm_soft_reset = 0;
-
- if (!adev->sdma.srbm_soft_reset)
- return 0;
-
- srbm_soft_reset = adev->sdma.srbm_soft_reset;
-
- if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
- REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
- sdma_v3_0_ctx_switch_enable(adev, false);
- sdma_v3_0_enable(adev, false);
- }
-
- return 0;
-}
-
-static int sdma_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- struct amdgpu_device *adev = ip_block->adev;
- u32 srbm_soft_reset = 0;
-
- if (!adev->sdma.srbm_soft_reset)
- return 0;
-
- srbm_soft_reset = adev->sdma.srbm_soft_reset;
-
- if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
- REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
- sdma_v3_0_gfx_resume(adev);
- sdma_v3_0_rlc_resume(adev);
- }
-
- return 0;
-}
-
static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
@@ -1552,9 +1494,6 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
.resume = sdma_v3_0_resume,
.is_idle = sdma_v3_0_is_idle,
.wait_for_idle = sdma_v3_0_wait_for_idle,
- .check_soft_reset = sdma_v3_0_check_soft_reset,
- .pre_soft_reset = sdma_v3_0_pre_soft_reset,
- .post_soft_reset = sdma_v3_0_post_soft_reset,
.soft_reset = sdma_v3_0_soft_reset,
.set_clockgating_state = sdma_v3_0_set_clockgating_state,
.set_powergating_state = sdma_v3_0_set_powergating_state,