diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 39 |
1 files changed, 14 insertions, 25 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index cbb74ffc4792..ad4d442e7345 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -848,6 +848,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, @@ -1455,7 +1456,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) { /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -1481,7 +1482,7 @@ static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 0xffffffff, 0xffffffff, xcc_id); mutex_unlock(&adev->grbm_idx_mutex); - DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", i, j); return; } @@ -1582,7 +1583,7 @@ static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); if (rlc_ucode_ver == 0x108) { dev_info(adev->dev, - "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", + "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", rlc_ucode_ver, adev->gfx.rlc_fw_version); /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, * default is 0x9C4 to create a 100us interval */ @@ -1666,12 +1667,12 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned vmid) +static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, + int inst, struct amdgpu_ring *ring, unsigned int vmid) { u32 reg, pre_data, data; - reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) pre_data = RREG32_NO_KIQ(reg); else @@ -1682,9 +1683,9 @@ static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu if (pre_data != data) { if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { - WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); } else - WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); } } @@ -2818,25 +2819,13 @@ static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), @@ -4914,7 +4903,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, adev->gfx.config.max_sh_per_se > 16) return -EINVAL; - amdgpu_gfx_parse_disable_cu(disable_masks, + amdgpu_gfx_parse_disable_cu(adev, disable_masks, adev->gfx.config.max_shader_engines, adev->gfx.config.max_sh_per_se); |