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-rw-r--r--arch/alpha/kernel/pci-sysfs.c32
-rw-r--r--arch/arm64/Kconfig9
-rw-r--r--arch/powerpc/kernel/pci-common.c9
3 files changed, 27 insertions, 23 deletions
diff --git a/arch/alpha/kernel/pci-sysfs.c b/arch/alpha/kernel/pci-sysfs.c
index 94dbc470cd6c..67f9822f7626 100644
--- a/arch/alpha/kernel/pci-sysfs.c
+++ b/arch/alpha/kernel/pci-sysfs.c
@@ -102,25 +102,25 @@ static int pci_mmap_resource_dense(struct file *filp, struct kobject *kobj,
return pci_mmap_resource(kobj, attr, vma, 0);
}
-#define __pci_dev_resource_attr(_bar, _name, _suffix, _mmap) \
-static const struct bin_attribute \
-pci_dev_resource##_bar##_suffix##_attr = { \
- .attr = { .name = __stringify(_name), .mode = 0600 }, \
- .private = (void *)(unsigned long)(_bar), \
- .mmap = (_mmap), \
+#define __pci_dev_resource_attr(_suffix, _bar, _name, _mmap) \
+static const struct bin_attribute \
+pci_dev_resource##_bar##_suffix##_attr = { \
+ .attr = { .name = __stringify(_name), .mode = 0600 }, \
+ .private = (void *)(unsigned long)(_bar), \
+ .mmap = (_mmap), \
}
-#define pci_dev_resource_attr(_bar) \
- __pci_dev_resource_attr(_bar, resource##_bar,, \
- pci_mmap_resource_dense)
+#define pci_dev_resource_attr(_bar) \
+ __pci_dev_resource_attr(, _bar, resource##_bar, \
+ pci_mmap_resource_dense)
#define pci_dev_resource_sparse_attr(_bar) \
- __pci_dev_resource_attr(_bar, resource##_bar##_sparse, _sparse, \
- pci_mmap_resource_sparse)
+ __pci_dev_resource_attr(_sparse, _bar, resource##_bar##_sparse, \
+ pci_mmap_resource_sparse)
#define pci_dev_resource_dense_attr(_bar) \
- __pci_dev_resource_attr(_bar, resource##_bar##_dense, _dense, \
- pci_mmap_resource_dense)
+ __pci_dev_resource_attr(_dense, _bar, resource##_bar##_dense, \
+ pci_mmap_resource_dense)
static int sparse_mem_mmap_fits(struct pci_dev *pdev, int num)
{
@@ -224,17 +224,17 @@ int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
switch(size) {
case 1:
- outb(port, val);
+ outb(val, port);
return 1;
case 2:
if (port & 1)
return -EINVAL;
- outw(port, val);
+ outw(val, port);
return 2;
case 4:
if (port & 3)
return -EINVAL;
- outl(port, val);
+ outl(val, port);
return 4;
}
return -EINVAL;
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a269f73b7653..b5a51b0ef944 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1427,6 +1427,15 @@ config NVIDIA_OLYMPUS_1027_ERRATUM
If unsure, say Y.
+config RENESAS_ERRATUM_GEN4GICITS1
+ bool "Renesas R-Car Gen4: GIC600 can not access physical addresses above 4 GiB"
+ default y
+ help
+ The Renesas R-Car Gen4 S4/V4H/V4M GIC600 SoC integrations have AXI
+ addressing limited to the first 32-bit of physical address space.
+
+ If unsure, say Y.
+
config ROCKCHIP_ERRATUM_3568002
bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
default y
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 3c4ca90e2ab7..4fc52c21fe5d 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -626,19 +626,14 @@ int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
return -ENXIO;
addr = hose->io_base_virt + port;
- /* WARNING: The generic code is idiotic. It gets passed a pointer
- * to what can be a 1, 2 or 4 byte quantity and always reads that
- * as a u32, which means that we have to correct the location of
- * the data read within those 32 bits for size 1 and 2
- */
switch(size) {
case 1:
- out_8(addr, val >> 24);
+ out_8(addr, val);
return 1;
case 2:
if (port & 1)
return -EINVAL;
- out_le16(addr, val >> 16);
+ out_le16(addr, val);
return 2;
case 4:
if (port & 3)