diff options
Diffstat (limited to 'Documentation/devicetree/bindings')
71 files changed, 1877 insertions, 538 deletions
diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml b/Documentation/devicetree/bindings/dpll/dpll-device.yaml index fb8d7a9a3693..4b5184500b9f 100644 --- a/Documentation/devicetree/bindings/dpll/dpll-device.yaml +++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml @@ -65,7 +65,7 @@ properties: const: 0 patternProperties: - "^pin@[0-9]+$": + "^pin@[0-9a-f]+$": $ref: /schemas/dpll/dpll-pin.yaml unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml index 23e92be33ac8..b12632545673 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml @@ -40,6 +40,9 @@ properties: description: PHY regulator + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 323a669fa982..2cae0133b3cd 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -21,6 +21,7 @@ select: - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun50i-h616-emac1 - allwinner,sun55i-a523-gmac200 required: - compatible @@ -33,6 +34,7 @@ properties: - const: allwinner,sun8i-r40-gmac - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac + - const: allwinner,sun50i-h616-emac1 - items: - enum: - allwinner,sun20i-d1-emac @@ -95,6 +97,17 @@ allOf: properties: compatible: contains: + const: allwinner,sun50i-h616-emac1 + + then: + properties: + phy-mode: + const: rmii + + - if: + properties: + compatible: + contains: enum: - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index db93436c96fa..ce1bd5f2c470 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -13,8 +13,6 @@ description: This binding describes the Altera SOCFPGA SoC implementation of the Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7 families of chips. - # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that - # does not validate against net/snps,dwmac.yaml. select: properties: @@ -158,6 +156,9 @@ properties: - description: offset of the control register - description: shift within the control register + power-domains: + maxItems: 1 + patternProperties: "^mdio[0-9]$": type: object diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 5c91716d1f21..9c9cc3ef384d 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -158,6 +158,9 @@ properties: interrupt-names: const: macirq + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/bluetooth/brcm,bluetooth.yaml b/Documentation/devicetree/bindings/net/bluetooth/brcm,bluetooth.yaml index 95501e858e6f..612d21123aaa 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/brcm,bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/brcm,bluetooth.yaml @@ -31,6 +31,7 @@ properties: - brcm,bcm43540-bt - brcm,bcm4335a0 - brcm,bcm4349-bt + - brcm,bcm4384-bt - cypress,cyw4373a0-bt - infineon,cyw55572-bt diff --git a/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml b/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml index a3db6d594c8c..7fcc564e820c 100644 --- a/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml +++ b/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml @@ -123,7 +123,7 @@ examples: phy0: ethernet-phy@1 { reg = <1>; }; - }; + }; mdio@ce14 { compatible = "brcm,asp-v2.1-mdio"; diff --git a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml index f0b5bea2458d..da9bc170cd54 100644 --- a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml @@ -87,18 +87,6 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/cortina,gemini-clock.h> #include <dt-bindings/reset/cortina,gemini-reset.h> - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - phy1: ethernet-phy@3 { - reg = <3>; - device_type = "ethernet-phy"; - }; - }; ethernet@60000000 { compatible = "cortina,gemini-ethernet"; @@ -110,28 +98,28 @@ examples: ranges; gmac0: ethernet-port@0 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ - <0x6000a000 0x2000>; /* Port 0 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC0>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; - clock-names = "PCLK"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; + compatible = "cortina,gemini-ethernet-port"; + reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ + <0x6000a000 0x2000>; /* Port 0 GMAC */ + interrupt-parent = <&intcon>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GMAC0>; + clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; + clock-names = "PCLK"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; }; gmac1: ethernet-port@1 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ - <0x6000e000 0x2000>; /* Port 1 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC1>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; - clock-names = "PCLK"; - phy-mode = "rgmii"; - phy-handle = <&phy1>; + compatible = "cortina,gemini-ethernet-port"; + reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ + <0x6000e000 0x2000>; /* Port 1 GMAC */ + interrupt-parent = <&intcon>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_GMAC1>; + clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; + clock-names = "PCLK"; + phy-mode = "rgmii"; + phy-handle = <&phy1>; }; }; diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index 8d4a3a9a33fc..4ed13870ed3a 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -23,6 +23,7 @@ properties: - microchip,ksz8864 # 4-port version of KSZ8895 family switch - microchip,ksz8873 - microchip,ksz8895 # 5-port version of KSZ8895 family switch + - microchip,ksz8995xa - microchip,ksz9477 - microchip,ksz9897 - microchip,ksz9896 diff --git a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml index 33a6552e46fc..93ba5b181205 100644 --- a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml +++ b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml @@ -21,6 +21,9 @@ description: | Any port can be used as the CPU port. + Each port has at most 3 LEDs connected and can be declared using the standard + LEDs structure. + properties: compatible: const: motorcomm,yt9215 @@ -59,6 +62,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> mdio { #address-cells = <1>; @@ -113,6 +117,25 @@ examples: label = "lan1"; phy-mode = "internal"; phy-handle = <&sw_phy0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; ethernet-port@1 { diff --git a/Documentation/devicetree/bindings/net/dsa/realtek.yaml b/Documentation/devicetree/bindings/net/dsa/realtek.yaml index 473facd87a62..b7bb60af623c 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek.yaml +++ b/Documentation/devicetree/bindings/net/dsa/realtek.yaml @@ -8,6 +8,20 @@ title: Realtek switches for unmanaged switches allOf: - $ref: dsa.yaml#/$defs/ethernet-ports + - if: + not: + properties: + compatible: + contains: + const: realtek,rtl8365mb + then: + properties: + avddh-supply: false + avddl-supply: false + dvddio-supply: false + dvddio1-supply: false + dvddl-supply: false + pllvddl-supply: false maintainers: - Linus Walleij <linusw@kernel.org> @@ -62,6 +76,24 @@ properties: resets: maxItems: 1 + avddh-supply: + description: AVDDH high-voltage analog supply. + + avddl-supply: + description: AVDDL low-voltage analog supply. + + dvddio-supply: + description: DVDDIO digital I/O supply. + + dvddio1-supply: + description: DVDDIO_1 secondary digital I/O supply for the RGMII bank. + + dvddl-supply: + description: DVDDL digital core supply. + + pllvddl-supply: + description: PLLVDDL PLL analog supply. + realtek,disable-leds: type: boolean description: | @@ -243,6 +275,7 @@ examples: platform { ethernet-switch { compatible = "realtek,rtl8365mb"; + avddh-supply = <&avddh>; mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml index ea285ef3e64f..fab6aa6237e9 100644 --- a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -127,8 +127,8 @@ examples: phy-mode = "internal"; fixed-link { - speed = <1000>; - full-duplex; + speed = <1000>; + full-duplex; }; }; }; diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index ba49fd6a086c..b79058b36d70 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -120,6 +120,9 @@ properties: - description: Optional offset of register controlling TXD delay - description: Optional offset of register controlling RXD delay + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 1bafd687dcb1..30b2a335116e 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -11,7 +11,7 @@ maintainers: properties: $nodename: - pattern: "^ethernet(@.*)?$" + pattern: "^ethernet(@.+|-[0-9]+)?$" label: description: Human readable label on a port of a box. diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index c3ebb3af8b52..df50c4c33d76 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -269,6 +269,22 @@ properties: have to be placed on board. When omitted, the PHYs default will be left as is. + marvell,reg-init: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + deprecated: true + description: + Register initialization tuples for Marvell PHYs. + items: + items: + - description: register page + maximum: 0xffff + - description: register number + maximum: 31 + - description: mask of bits to preserve + maximum: 0xffff + - description: value to apply + maximum: 0xffff + leds: type: object diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml index ef1e30a48c91..5dcb49f2f3b1 100644 --- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -125,10 +125,6 @@ required: - reg - fsl,fman-ports -dependencies: - pcs-handle-names: - - pcs-handle - allOf: - $ref: ethernet-controller.yaml# - if: diff --git a/Documentation/devicetree/bindings/net/hisilicon,hns-dsaf-v1.yaml b/Documentation/devicetree/bindings/net/hisilicon,hns-dsaf-v1.yaml new file mode 100644 index 000000000000..4629acbba810 --- /dev/null +++ b/Documentation/devicetree/bindings/net/hisilicon,hns-dsaf-v1.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Hisilicon Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hisilicon,hns-dsaf-v1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon DSA Fabric device controller + +maintainers: + - Jian Shen <shenjian15@huawei.com> + - Jijie Shao <shaojijie@huawei.com> + +properties: + compatible: + items: + - enum: + - hisilicon,hns-dsaf-v1 + - hisilicon,hns-dsaf-v2 + + reg: + minItems: 1 + items: + - description: + PPE register base and size + - description: + DSA Fabric base register and size (not required for single-port mode) + + reg-names: + minItems: 1 + items: + - const: ppe-base + - const: dsaf-base + + interrupts: + minItems: 1 + maxItems: 409 + + dma-coherent: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + mode: + description: DSA Fabric mode string + $ref: /schemas/types.yaml#/definitions/string + enum: + - 2port-64vf + - 6port-16rss + - 6port-16vf + - single-port + + subctrl-syscon: + description: syscon handle for external interface control register + $ref: /schemas/types.yaml#/definitions/phandle + + reset-field-offset: + description: offset of reset field in the control register + $ref: /schemas/types.yaml#/definitions/uint32 + + buf-size: + description: RX buffer size (bytes) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [512, 1024, 2048, 4096] + + desc-num: + description: number of descriptors in TX and RX queue + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 16 + maximum: 1024 + +patternProperties: + "^port@[0-5]$": + description: DSA Fabric port node + $ref: ethernet-switch-port.yaml# + additionalProperties: false + + properties: + reg: + maximum: 5 + + phy-handle: true + + serdes-syscon: + description: syscon handle for SerDes register + $ref: /schemas/types.yaml#/definitions/phandle + + cpld-syscon: + description: syscon handle plus register offset for CPLD register + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: CPLD phandle + - description: offset + + port-rst-offset: + description: reset field offset for this port + $ref: /schemas/types.yaml#/definitions/uint32 + + port-mode-offset: + description: port mode field offset for this port + $ref: /schemas/types.yaml#/definitions/uint32 + + mc-mac-mask: + description: multicast MAC address mask + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 6 + + media-type: + $ref: /schemas/types.yaml#/definitions/string + enum: + - backplane + - copper + - fiber + + required: + - reg + - serdes-syscon + +required: + - compatible + - reg + - reg-names + - interrupts + - subctrl-syscon + - mode + - buf-size + - desc-num + +additionalProperties: false + +examples: + - | + dsa@c5000000 { + compatible = "hisilicon,hns-dsaf-v1"; + #address-cells = <1>; + #size-cells = <0>; + mode = "6port-16rss"; + reg = <0xc5000000 0x890000 + 0xc7000000 0x60000>; + reg-names = "ppe-base", "dsaf-base"; + subctrl-syscon = <&subctrl>; + reset-field-offset = <0>; + interrupts = <131 4>, <132 4>, <133 4>, <134 4>, + <135 4>, <136 4>, <137 4>, <138 4>, + <139 4>, <140 4>, <141 4>, <142 4>, + <143 4>, <144 4>, <145 4>, <146 4>, + <147 4>, <148 4>, <384 1>, <385 1>, + <386 1>, <387 1>, <388 1>, <389 1>, + <390 1>, <391 1>; + buf-size = <4096>; + desc-num = <1024>; + dma-coherent; + + port@0 { + reg = <0>; + phy-handle = <&phy0>; + serdes-syscon = <&serdes>; + mc-mac-mask = [ff f0 00 00 00 00]; + }; + + port@1 { + reg = <1>; + serdes-syscon = <&serdes>; + mc-mac-mask = [ff f0 00 00 00 00]; + }; + }; diff --git a/Documentation/devicetree/bindings/net/hisilicon,hns-mdio.yaml b/Documentation/devicetree/bindings/net/hisilicon,hns-mdio.yaml new file mode 100644 index 000000000000..6904f9b351f2 --- /dev/null +++ b/Documentation/devicetree/bindings/net/hisilicon,hns-mdio.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hisilicon,hns-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HNS MDIO bus controller + +maintainers: + - Jian Shen <shenjian15@huawei.com> + - Jijie Shao <shaojijie@huawei.com> + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + enum: + - hisilicon,hns-mdio + - hisilicon,mdio + + reg: + maxItems: 1 + + subctrl-vbase: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: syscon phandle + - description: MDIO clock enable register offset + - description: MDIO reset request register offset + - description: MDIO clock state register offset + - description: MDIO reset state register offset + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - subctrl-vbase + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + mdio@803c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "hisilicon,hns-mdio"; + reg = <0x0 0x803c0000 0x0 0x10000>; + subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; + + ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/hisilicon,hns-nic.yaml b/Documentation/devicetree/bindings/net/hisilicon,hns-nic.yaml new file mode 100644 index 000000000000..799b3ef1e1eb --- /dev/null +++ b/Documentation/devicetree/bindings/net/hisilicon,hns-nic.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hisilicon,hns-nic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Network Subsystem NIC controller + +maintainers: + - Jian Shen <shenjian15@huawei.com> + - Jijie Shao <shaojijie@huawei.com> + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + enum: + - hisilicon,hns-nic-v1 + - hisilicon,hns-nic-v2 + + ae-handle: + description: + accelerator engine handle for hns, specifies a reference to the + associating hardware driver node. + $ref: /schemas/types.yaml#/definitions/phandle + + port-id: + description: | + is the index of port provided by DSAF (the accelerator). DSAF can connect to 8 PHYs. + Port 0 to 1 are both used for administration purpose. + They are called debug ports. + + The remaining 6 PHYs are taken according to the mode of DSAF. + + In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. + The port-id can be 2 to 7. Here is the diagram: + +-----+---------------+ + | CPU | + +-+-+-+---+-+-+-+-+-+-+ + | | | | | | | | + debug service + port port + (0,1) (2-7) + + In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a LAN Switch, + while the CPU side assume itself have one single NIC connect to this switch. + In this case, the port-id will be 2 only. + +-----+---------------+ + | CPU | + +-+-+-+---+-+-+-+-+-+-+ + | | service| port(2) + debug +------------+ + port | switch | + (0,1) +-+-+-+-+-+-++ + | | | | | | + external port + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 7 + deprecated: true + + port-idx-in-ae: + description: | + is the index of port provided by AE. + In NIC mode of DSAF, all 6 PHYs of service DSAF are taken as ethernet ports to the CPU. + The port-idx-in-ae can be 0 to 5. Here is the diagram: + +-----+---------------+ + | CPU | + +-+-+-+---+-+-+-+-+-+-+ + | | | | | | | | + debug debug service + port port port + (0) (0) (0-5) + + In Switch mode of DSAF, all 6 PHYs of service DSAF are taken as physical ports connected to + a LAN Switch, + while the CPU side assume itself have one single NIC connected to this switch. + In this case, the port-idx-in-ae will be 0 only. + +-----+-----+------+------+ + | CPU | + +-+-+-+-+-+-+-+-+-+-+-+-+-+ + | | service| port(0) + debug debug +------------+ + port port | switch | + (0) (0) +-+-+-+-+-+-++ + | | | | | | + external port + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + dma-coherent: true + +required: + - compatible + - ae-handle + - port-idx-in-ae + - local-mac-address + +unevaluatedProperties: false + +examples: + - | + ethernet { + compatible = "hisilicon,hns-nic-v1"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [a2 14 e4 4b 56 76]; + }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt deleted file mode 100644 index 8ee4b1cedae8..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt +++ /dev/null @@ -1,90 +0,0 @@ -Hisilicon DSA Fabric device controller - -Required properties: -- compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2". - "hisilicon,hns-dsaf-v1" is for hip05. - "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612. -- mode: dsa fabric mode string. only support one of dsaf modes like these: - "2port-64vf", - "6port-16rss", - "6port-16vf", - "single-port". -- interrupts: should contain the DSA Fabric and rcb interrupt. -- reg: specifies base physical address(es) and size of the device registers. - The first region is external interface control register base and size(optional, - only used when subctrl-syscon does not exist). It is recommended using - subctrl-syscon rather than this address. - The second region is SerDes base register and size(optional, only used when - serdes-syscon in port node does not exist). It is recommended using - serdes-syscon rather than this address. - The third region is the PPE register base and size. - The fourth region is dsa fabric base register and size. It is not required for - single-port mode. -- reg-names: may be ppe-base and(or) dsaf-base. It is used to find the - corresponding reg's index. - -- phy-handle: phy handle of physical port, 0 if not any phy device. It is optional - attribute. If port node exists, phy-handle in each port node will be used. - see ethernet.txt [1]. -- subctrl-syscon: is syscon handle for external interface control register. -- reset-field-offset: is offset of reset field. Its value depends on the hardware - user manual. -- buf-size: rx buffer size, should be 16-1024. -- desc-num: number of description in TX and RX queue, should be 512, 1024, 2048 or 4096. - -- port: subnodes of dsaf. A dsaf node may contain several port nodes(Depending - on mode of dsaf). Port node contain some attributes listed below: -- reg: is physical port index in one dsaf. -- phy-handle: phy handle of physical port. It is not required if there isn't - phy device. see ethernet.txt [1]. -- serdes-syscon: is syscon handle for SerDes register. -- cpld-syscon: is syscon handle + register offset pair for cpld register. It is - not required if there isn't cpld device. -- port-rst-offset: is offset of reset field for each port in dsaf. Its value - depends on the hardware user manual. -- port-mode-offset: is offset of port mode field for each port in dsaf. Its - value depends on the hardware user manual. -- mc-mac-mask: mask of multicast address, determines bit in multicast address - to set: - 1 stands for this bit will be precisely matched, TCAM will check this bit of - MAC address. - 0 stands for this bit will be fuzzy matched, TCAM won't care about this bit - of MAC address. - -[1] Documentation/devicetree/bindings/net/phy.txt - -Example: - -dsaf0: dsa@c7000000 { - compatible = "hisilicon,hns-dsaf-v1"; - mode = "6port-16rss"; - interrupt-parent = <&mbigen_dsa>; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x60000>; - reg-names = "ppe-base", "dsaf-base"; - subctrl-syscon = <&subctrl>; - reset-field-offset = 0; - interrupts = <131 4>,<132 4>, <133 4>,<134 4>, - <135 4>,<136 4>, <137 4>,<138 4>, - <139 4>,<140 4>, <141 4>,<142 4>, - <143 4>,<144 4>, <145 4>,<146 4>, - <147 4>,<148 4>, <384 1>,<385 1>, - <386 1>,<387 1>, <388 1>,<389 1>, - <390 1>,<391 1>, - buf-size = <4096>; - desc-num = <1024>; - dma-coherent; - - port@0 { - reg = 0; - phy-handle = <&phy0>; - serdes-syscon = <&serdes>; - mc-mac-mask = [ff f0 00 00 00 00]; - }; - - port@1 { - reg = 1; - serdes-syscon = <&serdes>; - mc-mac-mask = [ff f0 00 00 00 00]; - }; -}; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt deleted file mode 100644 index 4a7ede9657b0..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt +++ /dev/null @@ -1,27 +0,0 @@ -Hisilicon MDIO bus controller - -Properties: -- compatible: can be one of: - "hisilicon,hns-mdio" - "hisilicon,mdio" - "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs, - while "hisilicon,mdio" is optional for backwards compatibility only on - hip04 Soc. -- reg: The base address of the MDIO bus controller register bank. -- #address-cells: Must be <1>. -- #size-cells: Must be <0>. MDIO addresses have no size component. - -Typically an MDIO bus might have several children. - -Example: - mdio@803c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-mdio","hisilicon,mdio"; - reg = <0x0 0x803c0000 0x0 0x10000>; - - ethernet-phy@0 { - ... - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt deleted file mode 100644 index f0421ee3c714..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt +++ /dev/null @@ -1,76 +0,0 @@ -Hisilicon Network Subsystem NIC controller - -Required properties: -- compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2". - "hisilicon,hns-nic-v1" is for hip05. - "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612. -- ae-handle: accelerator engine handle for hns, - specifies a reference to the associating hardware driver node. - see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt -- port-id: is the index of port provided by DSAF (the accelerator). DSAF can - connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They - are called debug ports. - - The remaining 6 PHYs are taken according to the mode of DSAF. - - In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The - port-id can be 2 to 7. Here is the diagram: - +-----+---------------+ - | CPU | - +-+-+-+---+-+-+-+-+-+-+ - | | | | | | | | - debug service - port port - (0,1) (2-7) - - In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a - LAN Switch while the CPU side assume itself have one single NIC connect to - this switch. In this case, the port-id will be 2 only. - +-----+---------------+ - | CPU | - +-+-+-+---+-+-+-+-+-+-+ - | | service| port(2) - debug +------------+ - port | switch | - (0,1) +-+-+-+-+-+-++ - | | | | | | - external port - - This attribute is remained for compatible purpose. It is not recommended to - use it in new code. - -- port-idx-in-ae: is the index of port provided by AE. - In NIC mode of DSAF, all 6 PHYs of service DSAF are taken as ethernet ports - to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram: - +-----+---------------+ - | CPU | - +-+-+-+---+-+-+-+-+-+-+ - | | | | | | | | - debug debug service - port port port - (0) (0) (0-5) - - In Switch mode of DSAF, all 6 PHYs of service DSAF are taken as physical - ports connected to a LAN Switch while the CPU side assume itself have one - single NIC connected to this switch. In this case, the port-idx-in-ae - will be 0 only. - +-----+-----+------+------+ - | CPU | - +-+-+-+-+-+-+-+-+-+-+-+-+-+ - | | service| port(0) - debug debug +------------+ - port port | switch | - (0) (0) +-+-+-+-+-+-++ - | | | | | | - external port - -- local-mac-address: mac addr of the ethernet interface - -Example: - - ethernet@0{ - compatible = "hisilicon,hns-nic-v1"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [a2 14 e4 4b 56 76]; - }; diff --git a/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml b/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml index 62c1da36a2b5..81c123fe6bb9 100644 --- a/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml +++ b/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml @@ -47,6 +47,9 @@ properties: interrupt-names: const: macirq + power-domains: + maxItems: 1 + required: - compatible - clocks @@ -91,9 +94,9 @@ examples: snps,tx-queues-to-use = <2>; snps,tx-sched-wrr; queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; }; queue1 { diff --git a/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml b/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml index c4f3224bad38..c9a131b8d830 100644 --- a/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml +++ b/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml @@ -66,6 +66,9 @@ properties: - mii - rgmii-id + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml b/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml index 99001b940b83..49db18423dd8 100644 --- a/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml +++ b/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml @@ -65,6 +65,9 @@ properties: - mii - rmii + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.yaml b/Documentation/devicetree/bindings/net/mdio-gpio.yaml index eb4171a1940e..36e51aaae9c0 100644 --- a/Documentation/devicetree/bindings/net/mdio-gpio.yaml +++ b/Documentation/devicetree/bindings/net/mdio-gpio.yaml @@ -45,13 +45,13 @@ examples: }; mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qe_pio_a 11>, - <&qe_pio_c 6>; - ethphy0: ethernet-phy@0 { - reg = <0>; - }; + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&qe_pio_a 11>, + <&qe_pio_c 6>; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; }; ... diff --git a/Documentation/devicetree/bindings/net/micrel.yaml b/Documentation/devicetree/bindings/net/micrel.yaml index 6fa568057b92..a1f876dc00de 100644 --- a/Documentation/devicetree/bindings/net/micrel.yaml +++ b/Documentation/devicetree/bindings/net/micrel.yaml @@ -63,6 +63,14 @@ properties: minimum: 0 maximum: 3 + micrel,rmii-reference-clock-select-25-mhz: + enum: [ 1 ] + description: | + RMII Reference Clock Select bit selects 25 MHz mode. + + Setting the RMII Reference Clock Select bit enables 25 MHz rather + than 50 MHz clock mode. + allOf: - $ref: ethernet-phy.yaml# - if: @@ -91,6 +99,18 @@ allOf: properties: micrel,led-mode: false - if: + not: + properties: + compatible: + contains: + enum: + - ethernet-phy-id0022.1555 + - ethernet-phy-id0022.1556 + - ethernet-phy-id0022.1560 + then: + properties: + micrel,rmii-reference-clock-select-25-mhz: false + - if: properties: compatible: contains: @@ -105,13 +125,6 @@ allOf: description: The RMII reference input clock. Used to determine the XI input clock. - micrel,rmii-reference-clock-select-25-mhz: - type: boolean - description: | - RMII Reference Clock Select bit selects 25 MHz mode - - Setting the RMII Reference Clock Select bit enables 25 MHz rather - than 50 MHz clock mode. dependentRequired: micrel,rmii-reference-clock-select-25-mhz: [ clock-names ] diff --git a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml index 766ff58147ae..1b543ce30763 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml @@ -40,6 +40,11 @@ properties: Event. maxItems: 1 + reset-gpios: + description: + GPIO connected to the active-low RESET_N pin of the MAC-PHY. + maxItems: 1 + spi-max-frequency: minimum: 15000000 maximum: 25000000 diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml index 26688e2302ea..85d01690c856 100644 --- a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml @@ -15,6 +15,7 @@ allOf: properties: compatible: enum: + - ethernet-phy-id01e0.4281 - ethernet-phy-id4f51.e91a - ethernet-phy-id4f51.e91b diff --git a/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml b/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml index 86a9c3fc76c8..d825130b54b4 100644 --- a/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml +++ b/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml @@ -197,10 +197,10 @@ examples: <0x71040000 0x10000>, <0x71050000 0x10000>, <0x71060000 0x10000>; - reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", - "port2", "port3", "port4", "port5", "port6", - "port7", "port8", "port9", "port10", "qsys", - "ana", "s0", "s1", "s2"; + reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", + "port2", "port3", "port4", "port5", "port6", + "port7", "port8", "port9", "port10", "qsys", + "ana", "s0", "s1", "s2"; ethernet-ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml index ab18702e53f9..5301fe64e98b 100644 --- a/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml @@ -69,6 +69,9 @@ properties: items: - const: stmmaceth + power-domains: + maxItems: 1 + phy-mode: enum: - rmii diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml index 215f14d1897d..48e4798a039b 100644 --- a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml @@ -81,8 +81,9 @@ properties: phy-mode: contains: enum: - - usxgmii - 10gbase-kr + - 10gbase-r + - usxgmii mdio: $ref: mdio.yaml# @@ -90,6 +91,9 @@ properties: description: Optional node for embedded MDIO controller. +allOf: + - $ref: snps,dwmac-common.yaml# + required: - compatible - reg @@ -103,7 +107,7 @@ required: - phy-handle - phy-mode -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml index e5db346beca9..b240c76e7dd5 100644 --- a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml @@ -83,6 +83,9 @@ properties: description: To select RMII reference clock from external. + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml index 05acd9bc7616..f61188ab0dbe 100644 --- a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml @@ -51,6 +51,9 @@ properties: items: - const: stmmaceth + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 753a04941659..fcad2274302d 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -81,6 +81,9 @@ properties: - const: rx - const: ptp_ref + power-domains: + maxItems: 1 + required: - clocks - clock-names diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml new file mode 100644 index 000000000000..a331880eb11c --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/rockchip,rk3568-xpcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS + +maintainers: + - Coia Prant <coiaprant@gmail.com> + +description: | + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physical + Coding Sublayer (XPCS). + The PCS provides an interface between the Media Access Control (MAC) + and the Physical Medium Attachment (PMA) sublayer through a Media + Independent Interface (GMII). + + The XPCS is accessed over the APB3 bus and internally connected to a + Naneng Combo SerDes PHY. + It supports 1000BASE-X, SGMII and QSGMII modes. + +properties: + compatible: + const: rockchip,rk3568-xpcs + + reg: + maxItems: 1 + + clocks: + items: + - description: APB3 bus interface clock (clk_csr_i), required for register access + - description: EEE clock (clk_eee_i), required for Energy Efficient Ethernet operation + + clock-names: + items: + - const: csr + - const: eee + + phys: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - phys + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + #include <dt-bindings/power/rk3568-power.h> + #include <dt-bindings/phy/phy.h> + + ethernet-pcs@fda00000 { + compatible = "rockchip,rk3568-xpcs"; + reg = <0xfda00000 0x200000>; + clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "csr", "eee"; + phys = <&combphy2 PHY_TYPE_SGMII>; + power-domains = <&power RK3568_PD_PIPE>; + }; diff --git a/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml b/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml index 3bb32349c28c..526f8525bb4d 100644 --- a/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml +++ b/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml @@ -54,6 +54,12 @@ properties: - zyxel,gs1920-24hp-v2-pse - const: realtek,pse-mcu-gen1-smbus + # I2C, raw framing + - items: + - enum: + - ubnt,usw-lite-16-poe-pse + - const: realtek,pse-mcu-gen1-i2c + # UART - items: - enum: @@ -100,6 +106,7 @@ allOf: contains: enum: - realtek,pse-mcu-gen1-smbus + - realtek,pse-mcu-gen1-i2c - realtek,pse-mcu-gen2-smbus - realtek,pse-mcu-gen2-i2c then: diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index 423959cb928d..ef520f810577 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -86,6 +86,9 @@ properties: phy-names: const: serdes + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index 68ec76fe4473..38e3830512fe 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -246,14 +246,14 @@ examples: qcom,remote-pid = <5>; ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; }; ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml index 6d0b21a10732..96e9b9420892 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -74,9 +74,14 @@ description: | +------->| QCA8075 PHY | | PHY4 | | PHY5 | (clock) +-------------------------------------+ +-------+ +-------+ + The IPQ5424 PPE reuses the same switch core, but wires up only 3 + front panel ports (GMAC0-2) and the single EDMA FIFO interface; it + has no EIP FIFO and no ports 4-6. + properties: compatible: enum: + - qcom,ipq5424-ppe - qcom,ipq9574-ppe reg: @@ -105,24 +110,16 @@ properties: description: PPE switch miscellaneous interrupt interconnects: - items: - - description: Bus interconnect path leading to PPE switch core function - - description: Bus interconnect path leading to PPE register access - - description: Bus interconnect path leading to QoS generation - - description: Bus interconnect path leading to timeout reference - - description: Bus interconnect path leading to NSS NOC from memory NOC - - description: Bus interconnect path leading to memory NOC from NSS NOC - - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC + minItems: 5 + maxItems: 7 + description: + The number of interconnect paths depends on compatible, 5 paths for + qcom,ipq5424-ppe and 7 paths for qcom,ipq9574-ppe, enumerated in the + allOf conditionals below. interconnect-names: - items: - - const: ppe - - const: ppe_cfg - - const: qos_gen - - const: timeout_ref - - const: nssnoc_memnoc - - const: memnoc_nssnoc - - const: memnoc_nssnoc_1 + minItems: 5 + maxItems: 7 ethernet-dma: type: object @@ -144,8 +141,14 @@ properties: - const: apb resets: - maxItems: 1 - description: EDMA reset + items: + - description: EDMA system reset + - description: EDMA APB reset + + reset-names: + items: + - const: sys + - const: apb interrupts: minItems: 65 @@ -170,12 +173,13 @@ properties: - clocks - clock-names - resets + - reset-names - interrupts - interrupt-names ethernet-ports: patternProperties: - "^ethernet-port@[1-6]+$": + "^ethernet-port@[0-9a-f]+$": type: object unevaluatedProperties: false $ref: ethernet-switch-port.yaml# @@ -229,6 +233,61 @@ required: allOf: - $ref: ethernet-switch.yaml + - if: + properties: + compatible: + contains: + const: qcom,ipq9574-ppe + then: + properties: + interconnects: + items: + - description: Bus interconnect path leading to PPE switch core function + - description: Bus interconnect path leading to PPE register access + - description: Bus interconnect path leading to QoS generation + - description: Bus interconnect path leading to timeout reference + - description: Bus interconnect path leading to NSS NOC from memory NOC + - description: Bus interconnect path leading to memory NOC from NSS NOC + - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: qos_gen + - const: timeout_ref + - const: nssnoc_memnoc + - const: memnoc_nssnoc + - const: memnoc_nssnoc_1 + - if: + properties: + compatible: + contains: + const: qcom,ipq5424-ppe + then: + properties: + interconnects: + items: + - description: Bus interconnect path leading to PPE switch core function + - description: Bus interconnect path leading to PPE register access + - description: Bus interconnect path leading to CE AXI + - description: Bus interconnect path leading to CE APB + - description: Bus interconnect path leading to NSS CSR access + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: nssnoc_ce_axi + - const: nssnoc_ce_apb + - const: nssnoc_nss_csr + + ethernet-ports: + patternProperties: + "^ethernet-port@[0-9a-f]+$": + properties: + reg: + maximum: 3 unevaluatedProperties: false @@ -273,7 +332,10 @@ examples: <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; clock-names = "sys", "apb"; - resets = <&nsscc EDMA_HW_RESET>; + resets = <&nsscc PPE_EDMA_ARES>, + <&nsscc PPE_EDMA_CFG_ARES>; + reset-names = "sys", + "apb"; interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, diff --git a/Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml new file mode 100644 index 000000000000..5158481e5e5b --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,sa8255p-ethqos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ethernet ETHQOS device (firmware managed) + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Konrad Dybcio <konradybcio@kernel.org> + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: + dwmac based Qualcomm ethernet devices which support Gigabit + ethernet (version v2.3.0 and onwards) with clocks, interconnects, etc. + managed by firmware + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + const: qcom,sa8255p-ethqos + + reg: + maxItems: 2 + + reg-names: + items: + - const: stmmaceth + - const: rgmii + + interrupts: + items: + - description: Combined signal for various interrupt events + - description: The interrupt that occurs when HW safety error triggered + + interrupt-names: + items: + - const: macirq + - const: sfty + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: core + - const: mdio + + phys: + maxItems: 1 + + phy-names: + items: + - const: serdes + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg-names + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ethernet: ethernet@23040000 { + compatible = "qcom,sa8255p-ethqos"; + reg = <0x23040000 0x10000>, + <0x23056000 0x100>; + reg-names = "stmmaceth", "rgmii"; + + iommus = <&apps_smmu 0x120 0x7>; + + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "sfty"; + + dma-coherent; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + phy-handle = <ðernet_phy>; + phy-mode = "2500base-x"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + + power-domains = <&scmi8_pd 0>, <&scmi8_pd 1>; + power-domain-names = "core", "mdio"; + + phys = <&serdes1>; + phy-names = "serdes"; + }; diff --git a/Documentation/devicetree/bindings/net/realtek,rtl8224-package.yaml b/Documentation/devicetree/bindings/net/realtek,rtl8224-package.yaml new file mode 100644 index 000000000000..8e6500958ed1 --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek,rtl8224-package.yaml @@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl8224-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL8224 Ethernet PHY package + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Florian Fainelli <f.fainelli@gmail.com> + - Heiner Kallweit <hkallweit1@gmail.com> + +description: + The RTL8224 is a four-port 2.5Gbps Ethernet PHY. Its PHYs occupy four + consecutive MDIO addresses and share package-wide configuration registers. + + A package node is required when the first PHY's MDIO address is not a + multiple of four. Existing aligned layouts without a package node remain + supported. + + The package reg must identify the first physical PHY's MDIO address, + even if that PHY has no child node. Each child PHY reg is its absolute + MDIO address, not an offset from the package base. Unused PHY ports may + be omitted. The base address must not exceed 28, so that all four PHY + addresses fit within the MDIO address space. + + The enet-phy-pair-order and enet-phy-pair-polarity properties belong + to the individual PHY nodes and describe each port's MDI wiring. + +$ref: ethernet-phy-package.yaml# + +properties: + compatible: + const: realtek,rtl8224-package + + reg: + maximum: 28 + +patternProperties: + "^ethernet-phy@[a-f0-9]+$": + $ref: ethernet-phy.yaml# + + properties: + compatible: + const: ethernet-phy-ieee802.3-c45 + + leds: false + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + +# Enumerate the ranges because child addresses depend on the package base. +allOf: + - if: + properties: + reg: { const: 0 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 0, maximum: 3 } + - if: + properties: + reg: { const: 1 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 1, maximum: 4 } + - if: + properties: + reg: { const: 2 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 2, maximum: 5 } + - if: + properties: + reg: { const: 3 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 3, maximum: 6 } + - if: + properties: + reg: { const: 4 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 4, maximum: 7 } + - if: + properties: + reg: { const: 5 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 5, maximum: 8 } + - if: + properties: + reg: { const: 6 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 6, maximum: 9 } + - if: + properties: + reg: { const: 7 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 7, maximum: 10 } + - if: + properties: + reg: { const: 8 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 8, maximum: 11 } + - if: + properties: + reg: { const: 9 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 9, maximum: 12 } + - if: + properties: + reg: { const: 10 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 10, maximum: 13 } + - if: + properties: + reg: { const: 11 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 11, maximum: 14 } + - if: + properties: + reg: { const: 12 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 12, maximum: 15 } + - if: + properties: + reg: { const: 13 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 13, maximum: 16 } + - if: + properties: + reg: { const: 14 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 14, maximum: 17 } + - if: + properties: + reg: { const: 15 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 15, maximum: 18 } + - if: + properties: + reg: { const: 16 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 16, maximum: 19 } + - if: + properties: + reg: { const: 17 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 17, maximum: 20 } + - if: + properties: + reg: { const: 18 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 18, maximum: 21 } + - if: + properties: + reg: { const: 19 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 19, maximum: 22 } + - if: + properties: + reg: { const: 20 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 20, maximum: 23 } + - if: + properties: + reg: { const: 21 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 21, maximum: 24 } + - if: + properties: + reg: { const: 22 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 22, maximum: 25 } + - if: + properties: + reg: { const: 23 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 23, maximum: 26 } + - if: + properties: + reg: { const: 24 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 24, maximum: 27 } + - if: + properties: + reg: { const: 25 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 25, maximum: 28 } + - if: + properties: + reg: { const: 26 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 26, maximum: 29 } + - if: + properties: + reg: { const: 27 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 27, maximum: 30 } + - if: + properties: + reg: { const: 28 } + then: + patternProperties: + "^ethernet-phy@[a-f0-9]+$": + properties: + reg: { minimum: 28, maximum: 31 } + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package@1 { + compatible = "realtek,rtl8224-package"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <1>; + enet-phy-pair-order = <0>; + }; + + ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <2>; + enet-phy-pair-order = <0>; + }; + + ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <3>; + enet-phy-pair-order = <1>; + }; + + ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + enet-phy-pair-order = <1>; + enet-phy-pair-polarity = <0x1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml b/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml index 45033c31a2d5..07b39ef1fc62 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml @@ -91,8 +91,8 @@ examples: #size-cells = <0>; ethphy1: ethernet-phy@1 { - reg = <1>; - realtek,clkout-disable; - realtek,aldps-enable; + reg = <1>; + realtek,clkout-disable; + realtek,aldps-enable; }; }; diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml index 271e05bae9c5..139190e3f900 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Realtek RTL9300 MDIO Controller +title: Realtek Otto Switches Ethernet MDIO Controller maintainers: - Chris Packham <chris.packham@alliedtelesis.co.nz> @@ -14,6 +14,16 @@ properties: oneOf: - items: - enum: + - realtek,rtl8381-mdio + - realtek,rtl8382-mdio + - const: realtek,rtl8380-mdio + - items: + - enum: + - realtek,rtl8392-mdio + - realtek,rtl8393-mdio + - const: realtek,rtl8391-mdio + - items: + - enum: - realtek,rtl9302b-mdio - realtek,rtl9302c-mdio - realtek,rtl9303-mdio @@ -24,6 +34,8 @@ properties: - realtek,rtl9313-mdio - const: realtek,rtl9311-mdio - enum: + - realtek,rtl8380-mdio + - realtek,rtl8391-mdio - realtek,rtl9301-mdio - realtek,rtl9311-mdio @@ -59,6 +71,68 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl8380-mdio + - realtek,rtl8381-mdio + - realtek,rtl8382-mdio + then: + properties: + mdio-bus@0: + properties: + clock-frequency: + enum: [2500000, 10000000] + default: 2500000 + + patternProperties: + '^mdio-bus@[1-3]$': false + + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl8391-mdio + - realtek,rtl8392-mdio + - realtek,rtl8393-mdio + then: + patternProperties: + '^mdio-bus@[01]$': + properties: + clock-frequency: + enum: [1250000, 2500000, 5000000] + description: | + RTL839x has one clock selector shared by both MDIO buses. All explicitly + specified clock-frequency values must be identical. A bus without this + property inherits the shared frequency selected by another available bus. + If neither available bus specifies a frequency, 2500000 Hz is used. + + '^mdio-bus@[2-3]$': false + + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl9301-mdio + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - realtek,rtl9311-mdio + - realtek,rtl9312-mdio + - realtek,rtl9313-mdio + then: + patternProperties: + '^mdio-bus@[0-3]$': + properties: + clock-frequency: + enum: [1250000, 2500000, 5000000] + default: 2500000 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index 1e00ef5b3acd..fad002492421 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -97,6 +97,8 @@ properties: phy-handle: true + ptp-timer: true + '#address-cells': description: Number of address cells for the MDIO bus. const: 1 @@ -305,6 +307,15 @@ allOf: items: - const: fck - const: refclk + - if: + not: + properties: + compatible: + contains: + const: renesas,etheravb-rcar-gen4 + then: + properties: + ptp-timer: false additionalProperties: false diff --git a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml index 16dd7a2631ab..ed0d10a19ca4 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml @@ -44,6 +44,9 @@ properties: phandle pointing to a PCS sub-node compatible with renesas,rzn1-miic.yaml# + power-domains: + maxItems: 1 + required: - compatible diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index c8f76c8e7584..1c084aafa8f7 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -154,6 +154,9 @@ properties: Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml# (Refer RZ/T2H portion in the DT-binding file) + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml index 80c252845349..e8dda1961ab3 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -120,9 +120,18 @@ properties: maximum: 0x7F default: 0x10 + pcs-handle: + description: + Specifies a reference to a node representing the PCS device + connected to this GMAC. Required when phy-mode is "sgmii". + maxItems: 1 + phy-supply: description: PHY regulator + power-domains: + maxItems: 1 + required: - compatible - clocks @@ -159,6 +168,27 @@ allOf: clocks: minItems: 5 + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-gmac + then: + required: + - phy-mode + + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-gmac + phy-mode: + contains: + const: sgmii + then: + required: + - pcs-handle + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac-common.yaml b/Documentation/devicetree/bindings/net/snps,dwmac-common.yaml new file mode 100644 index 000000000000..a38ff314b3cd --- /dev/null +++ b/Documentation/devicetree/bindings/net/snps,dwmac-common.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/snps,dwmac-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare MAC common properties + +maintainers: + - Alexandre Torgue <alexandre.torgue@foss.st.com> + - Giuseppe Cavallaro <peppe.cavallaro@st.com> + - Jose Abreu <joabreu@synopsys.com> + +properties: + stmmac-axi-config: + type: object + unevaluatedProperties: false + description: + AXI BUS Mode parameters. + + properties: + snps,lpi_en: + $ref: /schemas/types.yaml#/definitions/flag + description: + enable Low Power Interface + + snps,xit_frm: + $ref: /schemas/types.yaml#/definitions/flag + description: + unlock on WoL + + snps,wr_osr_lmt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max write outstanding req. limit + + snps,rd_osr_lmt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max read outstanding req. limit + + snps,blen: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + this is a vector of supported burst length. + minItems: 7 + maxItems: 7 + + snps,fb: + $ref: /schemas/types.yaml#/definitions/flag + description: + fixed-burst + + snps,axi-config: + $ref: /schemas/types.yaml#/definitions/phandle + description: + AXI BUS Mode parameters. Phandle to a node that can contain the + following properties + * snps,lpi_en, enable Low Power Interface + * snps,xit_frm, unlock on WoL + * snps,wr_osr_lmt, max write outstanding req. limit + * snps,rd_osr_lmt, max read outstanding req. limit + * snps,blen, this is a vector of supported burst length. + * snps,fb, fixed-burst + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 2449311c6d28..2c4842404bf6 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -57,6 +57,7 @@ properties: - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun50i-h616-emac1 - amlogic,meson6-dwmac - amlogic,meson8b-dwmac - amlogic,meson8m2-dwmac @@ -72,6 +73,7 @@ properties: - nuvoton,ma35d1-dwmac - nxp,s32g2-dwmac - qcom,qcs404-ethqos + - qcom,sa8255p-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos @@ -119,6 +121,7 @@ properties: - starfive,jh7110-dwmac - tesla,fsd-ethqos - thead,th1520-gmac + - ultrarisc,dp1000-gmac reg: minItems: 1 @@ -174,7 +177,7 @@ properties: minItems: 1 items: - description: GMAC stmmaceth reset - - description: AHB reset + - description: AHB or OCP reset reset-names: oneOf: @@ -182,10 +185,11 @@ properties: - enum: [stmmaceth, ahb] - items: - const: stmmaceth - - const: ahb + - enum: [ahb, stmmaceth-ocp] power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 mac-mode: $ref: ethernet-controller.yaml#/properties/phy-connection-type @@ -195,18 +199,6 @@ properties: can be passive (no SW requirement), and requires that the MAC operate in a different mode than the PHY in order to function. - snps,axi-config: - $ref: /schemas/types.yaml#/definitions/phandle - description: - AXI BUS Mode parameters. Phandle to a node that can contain the - following properties - * snps,lpi_en, enable Low Power Interface - * snps,xit_frm, unlock on WoL - * snps,wr_osr_lmt, max write outstanding req. limit - * snps,rd_osr_lmt, max read outstanding req. limit - * snps,blen, this is a vector of supported burst length. - * snps,fb, fixed-burst - snps,mtl-rx-config: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -558,45 +550,6 @@ properties: required: - compatible - stmmac-axi-config: - type: object - unevaluatedProperties: false - description: - AXI BUS Mode parameters. - - properties: - snps,lpi_en: - $ref: /schemas/types.yaml#/definitions/flag - description: - enable Low Power Interface - - snps,xit_frm: - $ref: /schemas/types.yaml#/definitions/flag - description: - unlock on WoL - - snps,wr_osr_lmt: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - max write outstanding req. limit - - snps,rd_osr_lmt: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - max read outstanding req. limit - - snps,blen: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: - this is a vector of supported burst length. - minItems: 7 - maxItems: 7 - - snps,fb: - $ref: /schemas/types.yaml#/definitions/flag - description: - fixed-burst - required: - compatible - reg @@ -610,6 +563,7 @@ dependencies: allOf: - $ref: ethernet-controller.yaml# + - $ref: snps,dwmac-common.yaml# - if: properties: compatible: @@ -622,6 +576,7 @@ allOf: - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun50i-h616-emac1 - loongson,ls2k-dwmac - loongson,ls7a-dwmac - ingenic,jz4775-mac @@ -630,6 +585,7 @@ allOf: - ingenic,x1830-mac - ingenic,x2000-mac - qcom,qcs404-ethqos + - qcom,sa8255p-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml index 4eb63b303cff..8c8622160abb 100644 --- a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml @@ -121,22 +121,22 @@ examples: - | ether: ethernet@65000000 { compatible = "socionext,uniphier-ld20-ave4"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - }; - }; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + clock-names = "ether"; + clocks = <&sys_clk 6>; + reset-names = "ether"; + resets = <&sys_rst 6>; + socionext,syscon-phy-mode = <&soc_glue 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + }; }; + }; diff --git a/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml index b89456f0ef83..e78cbf594c69 100644 --- a/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml @@ -49,6 +49,9 @@ properties: reset-names: const: stmmaceth + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml index e8d3814db0e9..845e2c67d200 100644 --- a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml @@ -52,6 +52,9 @@ properties: interrupt-names: maxItems: 1 + power-domains: + maxItems: 1 + resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml index 678eccf044f9..9e0fb995327a 100644 --- a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml @@ -56,6 +56,9 @@ properties: reset-names: const: stmmaceth + power-domains: + maxItems: 1 + spacemit,apmu: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml index fdcc61c65f87..c424e7797392 100644 --- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml @@ -75,6 +75,9 @@ properties: The argument one is the offset of phy mode selection, the argument two is the shift of phy mode selection. + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 987254900d0d..29b878079ff0 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -121,6 +121,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml b/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml index dd7481bb16e5..ad635529d676 100644 --- a/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml +++ b/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml @@ -67,6 +67,9 @@ properties: - rgmii-rxid - rgmii-txid + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml index b3492a9aa4ef..c859f8bb5d58 100644 --- a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml @@ -78,6 +78,9 @@ properties: items: - const: macirq + power-domains: + maxItems: 1 + required: - clocks - clock-names diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml index 8b5da602a2e8..4d24dadfaa5d 100644 --- a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml +++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml @@ -192,50 +192,50 @@ examples: interrupt-names = "rx_thresh", "rx", "tx", "misc"; ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - label = "port1"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - phy-handle = <ðphy0_sw>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <1>; - }; - - cpsw_port2: port@2 { - reg = <2>; - label = "wan"; - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - phy-handle = <ðphy1_sw>; - phy-mode = "rgmii"; - ti,dual-emac-pvid = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + phy-handle = <ðphy0_sw>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <1>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "wan"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; + phy-handle = <ðphy1_sw>; + phy-mode = "rgmii"; + ti,dual-emac-pvid = <2>; + }; }; davinci_mdio_sw: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x1000 0x100>; - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - - ethphy0_sw: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1_sw: ethernet-phy@1 { - reg = <1>; - }; + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x1000 0x100>; + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + + ethphy0_sw: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1_sw: ethernet-phy@1 { + reg = <1>; + }; }; cpts { - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "cpts"; + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; + clock-names = "cpts"; }; }; diff --git a/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml b/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml index f0f32e18fc85..efa39eab0256 100644 --- a/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml @@ -48,6 +48,9 @@ properties: interrupt-names: const: macirq + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml new file mode 100644 index 000000000000..13029302877b --- /dev/null +++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 DWMAC Ethernet controller + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: + The DP1000 integrates a Synopsys DesignWare GMAC controller from the + 5.20 series. The SoC integration adds fixed RGMII TX and RX clock delays + which cannot be disabled. Consequently, a functional RGMII link requires + a PCB without TX or RX clock delays, represented by "rgmii-id". + +select: + properties: + compatible: + contains: + const: ultrarisc,dp1000-gmac + required: + - compatible + +properties: + compatible: + items: + - const: ultrarisc,dp1000-gmac + - const: snps,dwmac-5.20 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: stmmaceth + + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + + phy-mode: + const: rgmii-id + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + +allOf: + - $ref: snps,dwmac.yaml# + +unevaluatedProperties: false + +examples: + - | + ethernet@38000000 { + compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.20"; + reg = <0x38000000 0x1000000>; + clocks = <&clk 0>; + clock-names = "stmmaceth"; + interrupts = <84>; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + }; diff --git a/Documentation/devicetree/bindings/net/wireless/marvell,sd8787.yaml b/Documentation/devicetree/bindings/net/wireless/marvell,sd8787.yaml index 930b700b73d0..9f905ef5c2c0 100644 --- a/Documentation/devicetree/bindings/net/wireless/marvell,sd8787.yaml +++ b/Documentation/devicetree/bindings/net/wireless/marvell,sd8787.yaml @@ -59,6 +59,12 @@ properties: description: Calibration data for sub-band 3 in the 5GHz band. maxItems: 502 + marvell,invalid-reg-hint-in-rom: + $ref: /schemas/types.yaml#/definitions/flag + description: + The regulatory hint in ROM conflicts with platform configuration. + It should be ignored, so the platform regulatory domain can be used. + marvell,wakeup-pin: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml index ae6b97cdc44b..bf4116b057d2 100644 --- a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml +++ b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml @@ -325,22 +325,22 @@ examples: r0 { regdomain = "FCC"; txpower-5g { - b0 { - channels = <36 48>; - rates-ofdm = /bits/ 8 <23 23 23 23 23 23 23 23>; - rates-mcs = /bits/ 8 <1 23 23 23 23 23 23 23 23 23 23>, - /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22>; - rates-ru = /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22 22 22>, - /bits/ 8 <4 20 20 20 20 20 20 20 20 20 20 20 20>; - }; - b1 { - channels = <100 181>; - rates-ofdm = /bits/ 8 <14 14 14 14 14 14 14 14>; - rates-mcs = /bits/ 8 <4 14 14 14 14 14 14 14 14 14 14>; - txs-delta = <12 9 6>; - rates-ru = /bits/ 8 <7 14 14 14 14 14 14 14 14 14 14 14 14>; - }; - }; + b0 { + channels = <36 48>; + rates-ofdm = /bits/ 8 <23 23 23 23 23 23 23 23>; + rates-mcs = /bits/ 8 <1 23 23 23 23 23 23 23 23 23 23>, + /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22>; + rates-ru = /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22 22 22>, + /bits/ 8 <4 20 20 20 20 20 20 20 20 20 20 20 20>; + }; + b1 { + channels = <100 181>; + rates-ofdm = /bits/ 8 <14 14 14 14 14 14 14 14>; + rates-mcs = /bits/ 8 <4 14 14 14 14 14 14 14 14 14 14>; + txs-delta = <12 9 6>; + rates-ru = /bits/ 8 <7 14 14 14 14 14 14 14 14 14 14 14 14>; + }; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml index e667d78b3ab3..0cb065265df4 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml @@ -92,6 +92,22 @@ properties: ieee80211-freq-limit: true + nvmem-cells: + minItems: 1 + maxItems: 3 + description: + References to nvmem cells for MAC address and/or calibration data. + Supported cell names are mac-address, calibration, and pre-calibration. + + nvmem-cell-names: + minItems: 1 + maxItems: 3 + items: + enum: + - mac-address + - calibration + - pre-calibration + qcom,calibration-data: $ref: /schemas/types.yaml#/definitions/uint8-array description: @@ -408,4 +424,4 @@ examples: "msi15", "legacy"; ieee80211-freq-limit = <5470000 5875000>; - }; + }; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml index 589960144fe1..fa64c8aa56f5 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-wsi.yaml @@ -58,13 +58,6 @@ properties: String to uniquely identify variant of the calibration data for designs with colliding bus and device ids - qcom,ath12k-calibration-variant: - $ref: /schemas/types.yaml#/definitions/string - deprecated: true - description: - String to uniquely identify variant of the calibration data for designs - with colliding bus and device ids - qcom,wsi-controller: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml index 6c0888ae4c4e..60dfe257eadc 100644 --- a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml @@ -50,6 +50,9 @@ properties: used, this property is required. When SDIO is used, the "in-band" interrupt provided by the SDIO bus is used unless an interrupt is defined in the Device Tree. + + The hardware suffers from a limitation when this property is used with + SDIO. OOB IRQ with SDIO should only be used for debug. maxItems: 1 reset-gpios: diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt b/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt deleted file mode 100644 index 88fd28d15eac..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Texas Instruments wl1251 wireless lan controller - -The wl1251 chip can be connected via SPI or via SDIO. This -document describes the binding for the SPI connected chip. - -Required properties: -- compatible : Should be "ti,wl1251" -- reg : Chip select address of device -- spi-max-frequency : Maximum SPI clocking speed of device in Hz -- interrupts : Should contain interrupt line -- vio-supply : phandle to regulator providing VIO - -Optional properties: -- ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which - provides configuration data (calibration, MAC, ...) -- ti,power-gpio : GPIO connected to chip's PMEN pin if operated in - SPI mode -- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt - for optional SPI connection related properties, - -Examples: - -&spi1 { - wl1251@0 { - compatible = "ti,wl1251"; - - reg = <0>; - spi-max-frequency = <48000000>; - spi-cpol; - spi-cpha; - - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ - - vio-supply = <&vio>; - ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - }; -}; - -&mmc3 { - vmmc-supply = <&wlan_en>; - - bus-width = <4>; - non-removable; - ti,non-removable; - cap-power-off-card; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - - #address-cells = <1>; - #size-cells = <0>; - - wlan: wifi@1 { - compatible = "ti,wl1251"; - - reg = <1>; - - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */ - - ti,wl1251-has-eeprom; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wl1251.yaml b/Documentation/devicetree/bindings/net/wireless/ti,wl1251.yaml new file mode 100644 index 000000000000..6ce82c4a2c0b --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/ti,wl1251.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/ti,wl1251.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments WL1251 Wireless LAN Controller + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +properties: + compatible: + const: ti,wl1251 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vio-supply: + description: + Phandle to the regulator providing VIO. Required when connected via SPI. + + ti,power-gpio: + maxItems: 1 + description: + GPIO connected to chip's PMEN pin if operated in SPI mode. + + ti,wl1251-has-eeprom: + type: boolean + description: + The wl1251 has an EEPROM connected, which provides configuration + data (calibration, MAC, ...). + + clocks: + maxItems: 1 + + spi-max-frequency: true + spi-cpol: true + spi-cpha: true + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + wifi@0 { + compatible = "ti,wl1251"; + reg = <0>; + spi-max-frequency = <48000000>; + spi-cpol; + spi-cpha; + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_NONE>; + vio-supply = <&vio>; + ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + }; + }; + - | + #include <dt-bindings/interrupt-controller/irq.h> + mmc { + #address-cells = <1>; + #size-cells = <0>; + wifi@1 { + compatible = "ti,wl1251"; + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + ti,wl1251-has-eeprom; + }; + }; diff --git a/Documentation/devicetree/bindings/net/wiznet,w5100.yaml b/Documentation/devicetree/bindings/net/wiznet,w5100.yaml new file mode 100644 index 000000000000..b0d1e1d699dc --- /dev/null +++ b/Documentation/devicetree/bindings/net/wiznet,w5100.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wiznet,w5100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wiznet w5100/w5200/w5500 SPI Ethernet Controller + +maintainers: + - Arthur Crepin Leblond <arthur@marmottus.net> + +description: | + This is a standalone 10/100 MBit Ethernet controller with SPI interface. + +properties: + compatible: + enum: + - wiznet,w5100 + - wiznet,w5200 + - wiznet,w5500 + + interrupts: + minItems: 1 + description: + The main interrupt (INT pin) is mandatory on all devices. The w5500 + additionally supports an optional second interrupt for link status changes + (LINKLED pin). If it is not specified, link state changes will not be + reported. + items: + - description: Main interrupt (INT pin on the device). + - description: + Optional interrupt for link status changes (LINKLED pin on w5500). + + reg: + maxItems: 1 + + spi-max-frequency: + description: + According to the datasheets, w5500 and w5200 allow a maximum of 80 MHz + while w5100 is reported by users to allow a maximum of 14 MHz. However, + board designs may need to limit this value. + maximum: 80000000 + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - wiznet,w5500 + then: + properties: + interrupts: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + /* Example (for Raspberry Pi with pin control stuff for GPIO irq) */ + + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "wiznet,w5500"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>, + <24 IRQ_TYPE_EDGE_BOTH>; + local-mac-address = [ a0 b0 c0 d0 e0 f0 ]; + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + spi-max-frequency = <30000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/wiznet,w5x00.txt b/Documentation/devicetree/bindings/net/wiznet,w5x00.txt deleted file mode 100644 index e9665798c4be..000000000000 --- a/Documentation/devicetree/bindings/net/wiznet,w5x00.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Wiznet w5x00 - -This is a standalone 10/100 MBit Ethernet controller with SPI interface. - -For each device connected to a SPI bus, define a child node within -the SPI master node. - -Required properties: -- compatible: Should be one of the following strings: - "wiznet,w5100" - "wiznet,w5200" - "wiznet,w5500" -- reg: Specify the SPI chip select the chip is wired to. -- interrupts: Specify the interrupt index within the interrupt controller (referred - to above in interrupt-parent) and interrupt type. w5x00 natively - generates falling edge interrupts, however, additional board logic - might invert the signal. -- pinctrl-names: List of assigned state names, see pinctrl binding documentation. -- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line, - see also generic and your platform specific pinctrl binding - documentation. - -Optional properties: -- spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500. - According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however, - board designs may need to limit this value. -- local-mac-address: See ethernet.txt in the same directory. - - -Example (for Raspberry Pi with pin control stuff for GPIO irq): - -&spi { - ethernet@0: w5500@0 { - compatible = "wiznet,w5500"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <ð1_pins>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <30000000>; - }; -}; - -&gpio { - eth1_pins: eth1_pins { - brcm,pins = <25>; - brcm,function = <0>; /* in */ - brcm,pull = <0>; /* none */ - }; -}; diff --git a/Documentation/devicetree/bindings/net/x-powers,acx00-ephy-package.yaml b/Documentation/devicetree/bindings/net/x-powers,acx00-ephy-package.yaml new file mode 100644 index 000000000000..781695d9d9f1 --- /dev/null +++ b/Documentation/devicetree/bindings/net/x-powers,acx00-ephy-package.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/x-powers,acx00-ephy-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: X-Powers AC200 and AC300 Ethernet PHY packages + +maintainers: + - James Hilliard <james.hilliard1@gmail.com> + +description: + The AC200 and AC300 contain compatible Fast Ethernet PHY blocks which report + the same Clause 22 PHY ID and use the same link-side register layout. The + package control paths differ. AC200 package control registers are accessed + through the companion IC's I2C register interface, while AC300 control + registers occupy a second Clause 22 address fixed at 16 plus the link PHY + address. + + Systems with a known package use the corresponding AC200 or AC300 compatible. + Systems which can contain either package use the ACx00 compatible and a + packed NVMEM configuration field to select the backend at runtime. + + The link PHY cannot report its ID until the package control sequence has + completed, so its child node supplies the documented PHY ID. The package and + child use the same base address. The AC200 driver programs that address into + the package, while the AC300 driver derives its control address from it. + +properties: + compatible: + enum: + - x-powers,ac200-ephy-package + - x-powers,ac300-ephy-package + - x-powers,acx00-ephy-package + + reg: + maximum: 31 + + clocks: + maxItems: 1 + description: AC300 input clock, running at 24, 25, or 27 MHz + + vcc-supply: + description: + 3.3 V package supply. This is connected to EPHY_VCC on AC200 and VCC1 + on AC300. + + nvmem-cells: + maxItems: 1 + description: + Packed little-endian EPHY configuration value, with the least-significant + byte first. Bits 3 through 0 contain the analog calibration code, bits 7 + through 4 are reserved, bit 8 selects AC300 when set and AC200 when clear, + and bit 9 requests the AC300 low-calibration tuning sequence. Bits 15 + through 10 are reserved. + + AC300 and selectable ACx00 packages require the full configuration + field, including bits 8 and 9 even when their values are zero, returned + as two bytes. A fixed AC200 package may provide a one-byte calibration + value or a two-byte configuration with bit 8 clear, or omit the cell + and use its internal eFuse calibration copy. + + nvmem-cell-names: + const: configuration + + x-powers,ac200: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the AC200 companion IC described by the x-powers,ac200 MFD + binding. Its I2C interface provides access to the package control + registers used to power and configure the Ethernet PHY. + + x-powers,xmii-rx-clock-inverted: + type: boolean + description: + Invert the xMII receive clock inside the PHY. This is required by some + SoC integrations, including the Allwinner H6 AC200 connection. + +patternProperties: + ^ethernet-phy@[a-f0-9]+$: + $ref: ethernet-phy.yaml# + properties: + compatible: + const: ethernet-phy-id0044.1400 + required: + - compatible + unevaluatedProperties: false + +required: + - compatible + - vcc-supply + +dependentRequired: + nvmem-cells: [ nvmem-cell-names ] + +allOf: + - $ref: ethernet-phy-package.yaml# + - if: + properties: + compatible: + const: x-powers,ac200-ephy-package + then: + properties: + clocks: false + required: + - x-powers,ac200 + - if: + properties: + compatible: + const: x-powers,ac300-ephy-package + then: + properties: + x-powers,ac200: false + required: + - clocks + - nvmem-cells + - nvmem-cell-names + - if: + properties: + compatible: + const: x-powers,acx00-ephy-package + then: + required: + - clocks + - nvmem-cells + - nvmem-cell-names + - x-powers,ac200 + - if: + properties: + compatible: + enum: + - x-powers,ac300-ephy-package + - x-powers,acx00-ephy-package + then: + properties: + reg: + maximum: 7 + patternProperties: + ^ethernet-phy@[a-f0-9]+$: + properties: + reg: + maximum: 7 + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package@0 { + compatible = "x-powers,acx00-ephy-package"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pwm 5>; + vcc-supply = <®_3v3>; + nvmem-cells = <&ephy_configuration>; + nvmem-cell-names = "configuration"; + x-powers,ac200 = <&ac200>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id0044.1400"; + reg = <0>; + }; + }; + }; + +... |