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-rw-r--r--arch/x86/kernel/cpu/centaur.c35
-rw-r--r--arch/x86/kernel/cpu/common.c12
-rw-r--r--arch/x86/kernel/cpu/intel.c8
-rw-r--r--arch/x86/kernel/cpu/transmeta.c9
-rw-r--r--arch/x86/kernel/cpu/zhaoxin.c12
5 files changed, 39 insertions, 37 deletions
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 681d2da49341..513fa1f640f9 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -22,7 +22,7 @@
static void init_c3(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ u64 msr;
/* Test for Centaur Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) {
@@ -30,17 +30,17 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsr(MSR_VIA_FCR, lo, hi);
- lo |= ACE_FCR; /* enable ACE unit */
- wrmsr(MSR_VIA_FCR, lo, hi);
+ rdmsrq(MSR_VIA_FCR, msr);
+ /* enable ACE unit */
+ wrmsrq(MSR_VIA_FCR, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
}
/* enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsr(MSR_VIA_RNG, lo, hi);
- lo |= RNG_ENABLE; /* enable RNG unit */
- wrmsr(MSR_VIA_RNG, lo, hi);
+ rdmsrq(MSR_VIA_RNG, msr);
+ /* enable RNG unit */
+ wrmsrq(MSR_VIA_RNG, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
}
@@ -52,9 +52,8 @@ static void init_c3(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
/* Cyrix III family needs CX8 & PGE explicitly enabled. */
if (c->x86_model >= 6 && c->x86_model <= 13) {
- rdmsr(MSR_VIA_FCR, lo, hi);
- lo |= (1<<1 | 1<<7);
- wrmsr(MSR_VIA_FCR, lo, hi);
+ rdmsrq(MSR_VIA_FCR, msr);
+ wrmsrq(MSR_VIA_FCR, msr | (1 << 1 | 1 << 7));
set_cpu_cap(c, X86_FEATURE_CX8);
}
@@ -115,8 +114,9 @@ static void init_centaur(struct cpuinfo_x86 *c)
char *name;
u32 fcr_set = 0;
u32 fcr_clr = 0;
- u32 lo, hi, newlo;
+ u32 newlo;
u32 aa, bb, cc, dd;
+ struct msr val;
#endif
early_init_centaur(c);
init_intel_cacheinfo(c);
@@ -169,15 +169,16 @@ static void init_centaur(struct cpuinfo_x86 *c)
name = "??";
}
- rdmsr(MSR_IDT_FCR1, lo, hi);
- newlo = (lo|fcr_set) & (~fcr_clr);
+ rdmsrq(MSR_IDT_FCR1, val.q);
+ newlo = (val.l | fcr_set) & (~fcr_clr);
- if (newlo != lo) {
+ if (newlo != val.l) {
pr_info("Centaur FCR was 0x%X now 0x%X\n",
- lo, newlo);
- wrmsr(MSR_IDT_FCR1, newlo, hi);
+ val.l, newlo);
+ val.l = newlo;
+ wrmsrq(MSR_IDT_FCR1, val.q);
} else {
- pr_info("Centaur FCR is 0x%X\n", lo);
+ pr_info("Centaur FCR is 0x%X\n", val.l);
}
/* Emulate MTRRs using Centaur's MCR. */
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index a3df21d26460..cbef2c6c8478 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -339,16 +339,16 @@ bool cpuid_feature(void)
static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
- unsigned long lo, hi;
+ struct msr val;
if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
return;
/* Disable processor serial number: */
- rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
- lo |= 0x200000;
- wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
+ rdmsrq(MSR_IA32_BBL_CR_CTL, val.q);
+ val.l |= 0x200000;
+ wrmsrq(MSR_IA32_BBL_CR_CTL, val.q);
pr_notice("CPU serial number disabled.\n");
clear_cpu_cap(c, X86_FEATURE_PN);
@@ -2299,8 +2299,10 @@ static inline void idt_syscall_init(void)
/* May not be marked __init: used by software suspend */
void syscall_init(void)
{
+ struct msr val = { .h = (__USER32_CS << 16) | __KERNEL_CS };
+
/* The default user and kernel segments */
- wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
+ wrmsrq(MSR_STAR, val.q);
/*
* Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index abb3984336eb..076bdd0d3f85 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -542,12 +542,12 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
if (boot_cpu_has(X86_FEATURE_DS)) {
- unsigned int l1, l2;
+ u64 l;
- rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
- if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
+ rdmsrq(MSR_IA32_MISC_ENABLE, l);
+ if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_BTS);
- if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
+ if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_PEBS);
}
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index 1fdcd69c625c..c670fbb6ee50 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -24,7 +24,8 @@ static void early_init_transmeta(struct cpuinfo_x86 *c)
static void init_transmeta(struct cpuinfo_x86 *c)
{
- unsigned int cap_mask, uk, max, dummy;
+ u64 msr;
+ unsigned int max, dummy;
unsigned int cms_rev1, cms_rev2;
unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev;
char cpu_info[65];
@@ -86,10 +87,10 @@ static void init_transmeta(struct cpuinfo_x86 *c)
}
/* Unhide possibly hidden capability flags */
- rdmsr(0x80860004, cap_mask, uk);
- wrmsr(0x80860004, ~0, uk);
+ rdmsrq(0x80860004, msr);
+ wrmsrq(0x80860004, msr | ~0U);
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
- wrmsr(0x80860004, cap_mask, uk);
+ wrmsrq(0x80860004, msr);
/* All Transmeta CPUs have a constant TSC */
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 761aef5590ac..fe504fd43c77 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -21,7 +21,7 @@
static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ u64 msr;
/* Test for Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) {
@@ -29,19 +29,17 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ rdmsrq(MSR_ZHAOXIN_FCR57, msr);
/* Enable ACE unit */
- lo |= ACE_FCR;
- wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
}
/* Enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ rdmsrq(MSR_ZHAOXIN_FCR57, msr);
/* Enable RNG unit */
- lo |= RNG_ENABLE;
- wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
}