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-rw-r--r--Documentation/devicetree/bindings/w1/omap-hdq.txt22
-rw-r--r--Documentation/devicetree/bindings/w1/ti,hdq.yaml70
-rw-r--r--drivers/w1/masters/ds2482.c8
-rw-r--r--drivers/w1/slaves/w1_ds28e17.c8
4 files changed, 86 insertions, 22 deletions
diff --git a/Documentation/devicetree/bindings/w1/omap-hdq.txt b/Documentation/devicetree/bindings/w1/omap-hdq.txt
deleted file mode 100644
index 913c5f91a0f9..000000000000
--- a/Documentation/devicetree/bindings/w1/omap-hdq.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* OMAP HDQ One wire bus master controller
-
-Required properties:
-- compatible : should be "ti,omap3-1w" or "ti,am4372-hdq"
-- reg : Address and length of the register set for the device
-- interrupts : interrupt line.
-- ti,hwmods : "hdq1w"
-
-Optional properties:
-- ti,mode: should be "hdq": HDQ mode "1w": one-wire mode.
- If not specified HDQ mode is implied.
-
-Example:
-
-- From omap3.dtsi
- hdqw1w: 1w@480b2000 {
- compatible = "ti,omap3-1w";
- reg = <0x480b2000 0x1000>;
- interrupts = <58>;
- ti,hwmods = "hdq1w";
- ti,mode = "hdq";
- };
diff --git a/Documentation/devicetree/bindings/w1/ti,hdq.yaml b/Documentation/devicetree/bindings/w1/ti,hdq.yaml
new file mode 100644
index 000000000000..fd402c0510db
--- /dev/null
+++ b/Documentation/devicetree/bindings/w1/ti,hdq.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/w1/ti,hdq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments OMAP HDQ One Wire Bus Master Controller
+
+maintainers:
+ - Eduard Bostina <egbostina@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,omap3-1w
+ - ti,am4372-hdq
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: fck
+
+ ti,hwmods:
+ description: Name of the hwmod associated to the hdq
+ $ref: /schemas/types.yaml#/definitions/string
+ const: hdq1w
+
+ ti,mode:
+ description: |
+ Operation mode. "hdq" for HDQ mode, "1w" for One-Wire mode.
+ If not specified, HDQ mode is implied.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - hdq
+ - 1w
+ default: hdq
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ onewire@0 {
+ compatible = "ti,am4372-hdq";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&func_12m_clk>;
+ clock-names = "fck";
+ };
+ - |
+ onewire@480b2000 {
+ compatible = "ti,omap3-1w";
+ reg = <0x480b2000 0x1000>;
+ interrupts = <58>;
+ ti,hwmods = "hdq1w";
+ ti,mode = "hdq";
+ };
diff --git a/drivers/w1/masters/ds2482.c b/drivers/w1/masters/ds2482.c
index 0069e6f854d7..9e57c6e487d1 100644
--- a/drivers/w1/masters/ds2482.c
+++ b/drivers/w1/masters/ds2482.c
@@ -545,9 +545,17 @@ static const struct i2c_device_id ds2482_id[] = {
};
MODULE_DEVICE_TABLE(i2c, ds2482_id);
+static const struct of_device_id ds2482_of_match[] = {
+ { .compatible = "maxim,ds2482", },
+ { .compatible = "maxim,ds2484", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ds2482_of_match);
+
static struct i2c_driver ds2482_driver = {
.driver = {
.name = "ds2482",
+ .of_match_table = ds2482_of_match,
},
.probe = ds2482_probe,
.remove = ds2482_remove,
diff --git a/drivers/w1/slaves/w1_ds28e17.c b/drivers/w1/slaves/w1_ds28e17.c
index e53bc41bde3c..b638963d4b59 100644
--- a/drivers/w1/slaves/w1_ds28e17.c
+++ b/drivers/w1/slaves/w1_ds28e17.c
@@ -389,6 +389,10 @@ static int w1_f19_i2c_master_transfer(struct i2c_adapter *adapter,
* another simple read in that case.
*/
if (msgs[i+1].flags & I2C_M_RECV_LEN) {
+ if (msgs[i+1].buf[0] > I2C_SMBUS_BLOCK_MAX) {
+ i = -EPROTO;
+ goto error;
+ }
result = w1_f19_i2c_read(sl, msgs[i+1].addr,
&(msgs[i+1].buf[1]), msgs[i+1].buf[0]);
if (result < 0) {
@@ -415,6 +419,10 @@ static int w1_f19_i2c_master_transfer(struct i2c_adapter *adapter,
* another simple read in that case.
*/
if (msgs[i].flags & I2C_M_RECV_LEN) {
+ if (msgs[i].buf[0] > I2C_SMBUS_BLOCK_MAX) {
+ i = -EPROTO;
+ goto error;
+ }
result = w1_f19_i2c_read(sl,
msgs[i].addr,
&(msgs[i].buf[1]),