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| author | Maciej S. Szmigiero <maciej.szmigiero@oracle.com> | 2025-12-05 14:49:37 -0800 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2026-01-08 10:50:50 -0800 |
| commit | 0b28194c4c8e3a6c2552bfa6451f71b1879dd61f (patch) | |
| tree | b25c7d081c0566e7efd3c8a1f2912cd719b6776f /tools/testing/selftests/kvm/include/x86 | |
| parent | 9ace4753a5202b02191d54e9fdf7f9e3d02b85eb (diff) | |
| download | linux-next-0b28194c4c8e3a6c2552bfa6451f71b1879dd61f.tar.gz linux-next-0b28194c4c8e3a6c2552bfa6451f71b1879dd61f.zip | |
KVM: selftests: Test TPR / CR8 sync and interrupt masking
Add a few extra TPR / CR8 tests to x86's xapic_state_test to see if:
* TPR is 0 on reset,
* TPR, PPR and CR8 are equal inside the guest,
* TPR and CR8 read equal by the host after a VMExit
* TPR borderline values set by the host correctly mask interrupts in the
guest.
These hopefully will catch the most obvious cases of improper TPR sync or
interrupt masking.
Do these tests both in x2APIC and xAPIC modes.
The x2APIC mode uses SELF_IPI register to trigger interrupts to give it a
bit of exercise too.
Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Acked-by: Naveen N Rao (AMD) <naveen@kernel.org>
[sean: put code in separate test]
Link: https://patch.msgid.link/20251205224937.428122-1-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools/testing/selftests/kvm/include/x86')
| -rw-r--r-- | tools/testing/selftests/kvm/include/x86/apic.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tools/testing/selftests/kvm/include/x86/apic.h b/tools/testing/selftests/kvm/include/x86/apic.h index 80fe9f69b38d..e9b9aebaac97 100644 --- a/tools/testing/selftests/kvm/include/x86/apic.h +++ b/tools/testing/selftests/kvm/include/x86/apic.h @@ -28,6 +28,8 @@ #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF) #define APIC_TASKPRI 0x80 #define APIC_PROCPRI 0xA0 +#define GET_APIC_PRI(x) (((x) & GENMASK(7, 4)) >> 4) +#define SET_APIC_PRI(x, y) (((x) & ~GENMASK(7, 4)) | (y << 4)) #define APIC_EOI 0xB0 #define APIC_SPIV 0xF0 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) @@ -67,6 +69,7 @@ #define APIC_TMICT 0x380 #define APIC_TMCCT 0x390 #define APIC_TDCR 0x3E0 +#define APIC_SELF_IPI 0x3F0 void apic_disable(void); void xapic_enable(void); |