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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-09-17 09:52:32 +0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2026-09-22 11:37:00 +0200 |
| commit | ff1621adfdd7cfb73f2ccdd3856cd3462ac98ac5 (patch) | |
| tree | e2cfbfbad8728c2b0da43fe669ac015f06e5df77 /tools/perf/scripts/python | |
| parent | 04a7ef3b7aa3af34202285043e3423a2e3983595 (diff) | |
| download | linux-next-ff1621adfdd7cfb73f2ccdd3856cd3462ac98ac5.tar.gz linux-next-ff1621adfdd7cfb73f2ccdd3856cd3462ac98ac5.zip | |
perf/x86/intel: Fix precise OMR event scheduling for DMR/NVL
The latest perfmon event database introduces below precise OMR event
support for DMR/NVL:
- MEM_LOAD_L2_MISS_RETIRED.* (event 0xd6)
- MEM_STORE_L2_MISS_RETIRED.* (event 0x4f)
These events use the same OMR MSRs as the existing OMR events, but
they are not listed in intel_pnc_extra_regs[]. As a result, perf
cannot assign the required OMR extra registers when scheduling them.
Add the new precise OMR events to intel_pnc_extra_regs[] so they can
be scheduled with the correct OMR MSRs. MEM_LOAD_L2_MISS_RETIRED.*
remains limited to GP counters 0-3, while
MEM_STORE_L2_MISS_RETIRED.* is available on all GP counters.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260917015234.981153-11-dapeng1.mi@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions