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authorDave Jiang <dave.jiang@intel.com>2026-09-17 20:06:02 -0700
committerDave Jiang <dave.jiang@intel.com>2026-09-17 20:06:02 -0700
commite6c4de5c1fde09a42d7d7475e1500f23da33c9a1 (patch)
treee7e91fb54011d303b85a0cf04e1b635f944ea64c /tools/perf/scripts/python
parentfd73f4a6659897191fa0d40695fe370925dd3780 (diff)
parentbb26797c08d408ea7e8d3625045f0fe28714a425 (diff)
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Merge branch 'for-7.4/cxl-fixes' into cxl-for-next
cxl/region: Unregister the pmem region when the bridge is unbound cxl/core: Fix dport use-after-free via the einj_inject debugfs file cxl/port: Fix uninitialized coordinates reported for RCDs cxl/cdat: Fix uninitialized stack use in bandwidth gathering cxl/features: Ensure that count is set before access to ent[] __counted_by() cxl/pci: Skip reset detection for DVSEC emulated decoders cxl/fwctl: Propagate feature RPC delivery errors cxl/features: Reject feature offset that overflows 16-bit field cxl/ras: Pass the PCI device's struct device to match_memdev_by_parent() cxl/test: Map mock device nodes to an online node cxl/mce: Avoid alias page retirement for corrected errors cxl/test: Don't wrap cxl_core's own exported symbols
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