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| author | Malathi A <malathi.a2000@gmail.com> | 2026-09-17 04:05:09 +0000 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-09-23 14:48:23 +0200 |
| commit | 790aacba3fdfd3a227cdd5e4952c596ed66a0ed8 (patch) | |
| tree | 2d932e590d80cf121d9795808afdc655e0616b74 /tools/perf/scripts/python | |
| parent | c5b33c86d86da3ccff8c05e2a28719e3ec933f70 (diff) | |
| download | linux-next-790aacba3fdfd3a227cdd5e4952c596ed66a0ed8.tar.gz linux-next-790aacba3fdfd3a227cdd5e4952c596ed66a0ed8.zip | |
serial: 8250_uniphier: Use devm_clk_get_enabled()
uniphier_uart_probe() enables priv->clk by hand and is then responsible
for disabling it again on every error path. It misses one: when
uart_read_port_properties() fails the function returns directly, leaving
the clock prepared and enabled. The neighbouring path, taken when
serial8250_register_8250_port() fails, does call clk_disable_unprepare(),
which shows the leak is an oversight rather than intent.
Rather than adding another manual unwind, switch to
devm_clk_get_enabled() so the clock is released by devres. That removes
the error path entirely, along with the explicit disables in the
register failure path and in uniphier_uart_remove().
The clock is still disabled and re-enabled by hand across system sleep,
which stays balanced: only SET_SYSTEM_SLEEP_PM_OPS is used, so the
device cannot be unbound while suspended and devres always sees an
enabled clock at detach.
Found by smatch:
drivers/tty/serial/8250/8250_uniphier.c:232 uniphier_uart_probe() warn: 'priv->clk' from clk_prepare_enable() not released on lines: 205.
Fixes: 26e8349c0d76 ("serial: 8250_uniphier: Switch to use uart_read_port_properties()")
Signed-off-by: Malathi A <malathi.a2000@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260917040511.103232-1-malathi.a2000@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
