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| author | Alison Schofield <alison.schofield@intel.com> | 2026-08-07 17:05:49 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-09-16 09:05:11 -0700 |
| commit | 3f846646b3d3b5699139e686e1107d231a725860 (patch) | |
| tree | 67e0019a7a355fe21291c78439d4f45a6f730dab /tools/perf/scripts/python/task-analyzer.py | |
| parent | 3696326ca14cf018788d64232a068fdf26b1ff31 (diff) | |
| download | linux-next-3f846646b3d3b5699139e686e1107d231a725860.tar.gz linux-next-3f846646b3d3b5699139e686e1107d231a725860.zip | |
cxl/hdm: Make switch decoder target parsing endian-safe
Switch decoder target IDs are stored one per byte, starting with
target 0 in the least significant byte. The current code accesses
those bytes in memory order, which only matches register order on
little-endian hosts.
On big-endian hosts, the target IDs are reversed and the decoder is
associated with the wrong downstream ports.
Place the register values in a byte array in little-endian order and
index the target IDs from there, so the target mapping is independent
of host endianness.
Fixes: d17d0540a0db ("cxl/core/hdm: Add CXL standard decoder enumeration to the core")
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Link: https://patch.msgid.link/b0526825b3c3ffdb78837563e178d9aa27b6bbb8.1786143520.git.alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions