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| author | Bean Huo <beanhuo@micron.com> | 2026-09-04 12:51:55 +0200 |
|---|---|---|
| committer | Keith Busch <kbusch@kernel.org> | 2026-09-11 07:39:31 -0700 |
| commit | c72f9f7bd23c91e944910d9bcbf12503d21a4a1f (patch) | |
| tree | 27c3afc5848b7b887ee778b76d54395b61ad48ca /tools/perf/scripts/python/stackcollapse.py | |
| parent | 5067d4ba713961d8ccea1e06cd4c453793f3121e (diff) | |
| download | linux-next-c72f9f7bd23c91e944910d9bcbf12503d21a4a1f.tar.gz linux-next-c72f9f7bd23c91e944910d9bcbf12503d21a4a1f.zip | |
nvme-pci: add NVME_QUIRK_DMAPOOL_ALIGN_512 for Micron 4100AT
The Micron 4100AT fetches PRP Lists in 512 byte strides, but the driver
allocates small PRP List descriptors in 256 byte strides. A descriptor
in the last 256 bytes of a dmapool page makes the controller read past
the page: the access lands on an adjacent IOVA, the IOMMU faults the
command. That last block only became reachable with commit da9619a30e73
("dmapool: link blocks across pages"), so this affects v6.4 and later.
Align the small descriptor pool to 512 bytes, as commit ebefac564796
("nvme-pci: 512 byte aligned dma pool segment quirk") already does for
another controller with the same erratum. The last block then starts
at offset 0xE00 and the fetch stays inside the page.
Cc: <stable@vger.kernel.org> # 6.4.x: ebefac564796: nvme-pci: 512 byte aligned dma pool segment quirk
Cc: <stable@vger.kernel.org> # 6.4.x
Signed-off-by: Gaurav Sinha <gsinha@micron.com>
Signed-off-by: Bean Huo <beanhuo@micron.com>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions