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| author | Andre Przywara <andre.przywara@arm.com> | 2026-09-10 15:35:14 +0200 |
|---|---|---|
| committer | Linus Walleij <linusw@kernel.org> | 2026-09-16 19:09:15 +0200 |
| commit | 8b367fc08be4d7fe7892db4351bf8bc51682ac1b (patch) | |
| tree | ec7a8f865123870deafa7ac1f0e05324e748888d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 149d4c5c98d5803ad33d169932378be7e68fedc8 (diff) | |
| download | linux-next-8b367fc08be4d7fe7892db4351bf8bc51682ac1b.tar.gz linux-next-8b367fc08be4d7fe7892db4351bf8bc51682ac1b.zip | |
pinctrl: sunxi: refactor IRQ register accessors
So far on Allwinner SoCs the registers for controlling the IRQ
capabilities of each bank are grouped separately, behind all the pinmux
related register for all banks:
0x000 0x024 0x144 0x200 0x220 0x320
PortA PortB ... PortJ <gap> IRQ-A IRQ-B ... IRQ-J
The newest SoCs now group the IRQ registers together with the other
per-bank registers, so we need to change the accessor functions to
account for that:
0x080 0x0c0 0x100 0x140 0x580 0x5c0
PortA IRQ-A PortB IRQ-B ... PortK IRQ-K
In preparation for supporting those newer SoCs, pass in the pointer to
"struct sunxi_pinctrl" instead of just its member "desc", so that we gain
access to the flags, to later determine which of the layout variants we
need to use. To simplify that, add a new sunxi_irq_base_reg() function
that returns the respective IRQ register base address.
Also split off the IRQ control register base offset (0x200) from each
IRQ register's offset, so that the individual offsets can be added later
separately, to that base address.
No functional change at this point, just refactoring.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
