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authorRupesh Majhi <zoone.rupert@gmail.com>2026-09-21 21:31:23 +0300
committerJonathan Cameron <jonathan.cameron@oss.qualcomm.com>2026-09-28 17:07:37 +0100
commit4334dc4092c271e6cd010c2ee70b7f4415c4c199 (patch)
tree63af222c19e86b645187e6ddc24d1c3b798f4178 /tools/perf/scripts/python/stackcollapse.py
parentb96187644664d10b641dddeb7ca2eeef97a77c41 (diff)
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iio: pressure: dps310: fix CFG_REG bit definitions
Driver defines them as BIT(4), BIT(5) and BIT(6). Per datasheet P_SHIFT is bit 2, FIFO_EN is bit 1 and SPI_MODE is bit 0. Only P_SHIFT has a user. dps310_set_pres_precision() sets it at oversampling 16 or above, so with wrong bit the result register is never shifted and stops matching the scale factor compensation divides by. in_pressure_input returns -ERANGE at oversampling 16, 32 and 64. FIFO_EN needed by FIFO support later in this series. Fixes: ba6ec48e76bc ("iio: Add driver for Infineon DPS310") Fixes: d711a3c7dc82 ("iio: dps310: Add pressure sensing capability") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Rupesh Majhi <zoone.rupert@gmail.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
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