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| author | Alison Schofield <alison.schofield@intel.com> | 2026-08-07 17:05:48 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-09-16 09:05:11 -0700 |
| commit | 3696326ca14cf018788d64232a068fdf26b1ff31 (patch) | |
| tree | c6e44fa15efdba66b9f79cb0e5d97c5959cbe68b /tools/perf/scripts/python/stackcollapse.py | |
| parent | fd73f4a6659897191fa0d40695fe370925dd3780 (diff) | |
| download | linux-next-3696326ca14cf018788d64232a068fdf26b1ff31.tar.gz linux-next-3696326ca14cf018788d64232a068fdf26b1ff31.zip | |
cxl/hdm: Reject switch decoder interleave ways that overflow targets
Switch decoder enumeration validates that the interleave ways encoding
is legal, but not that the resulting number of ways fits the available
targets. This can overrun the target array (target_list.target_id[])
during enumeration of 12 or 16 way interleaves.
Bound the target count where it is established rather than at each use.
Reject an HDM capability whose reported target count is zero or exceeds
the target list register capacity, and reject a zero target switch
decoder allocation in cxl_switch_decoder_init(). Enumeration is then
left with a single check: reject a decoder whose interleave ways exceed
the targets it has.
Add a clarifying comment that target_count is a direct count, not
0-based like decoder_count.
Link: https://sashiko.dev/#/patchset/20260711180755.1779002-1-alison.schofield@intel.com?part=1
Fixes: d17d0540a0db ("cxl/core/hdm: Add CXL standard decoder enumeration to the core")
Tested-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Link: https://patch.msgid.link/af094094813d7f51d86cbf608936270b7d85526e.1786143520.git.alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
