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authorJia Wang <wangjia@ultrarisc.com>2026-09-02 17:26:13 +0800
committerVinod Koul <vkoul@kernel.org>2026-09-10 19:27:22 +0530
commit2a9013c20c46216b92ff09e2283b5244a91c59da (patch)
treecea6255e80f82caf413c7c0f77f44b4e4f345a7a /tools/perf/scripts/python/stackcollapse.py
parente6b49f8016ee8b642e8e495d1704342ee0b35d72 (diff)
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dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position
The CH_CFG2 channel priority field occupies bits 51:47 of the 64-bit channel configuration register, corresponding to bits 19:15 of CH_CFG2_H. The driver currently shifts the priority value by 20, programming the wrong bits. Use bit 15 as the field position. Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8") Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260902-dma-fix-v3-3-414c6449fbcc@ultrarisc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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