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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-09-17 09:52:31 +0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2026-09-22 11:35:40 +0200 |
| commit | 04a7ef3b7aa3af34202285043e3423a2e3983595 (patch) | |
| tree | cdb04b6a5e9a340677aafd154ebbdec81a9bf02f /tools/perf/scripts/python/bin/task-analyzer-record | |
| parent | 858b37ca19d3f695f7fa94cd14be5a856fd8e7d7 (diff) | |
| download | linux-next-04a7ef3b7aa3af34202285043e3423a2e3983595.tar.gz linux-next-04a7ef3b7aa3af34202285043e3423a2e3983595.zip | |
perf/x86/intel: Constrain Panther Cove UOPS_DISPATCHED events to PMCs 0-3
Per the latest Panther Cove event definitions, the following events are
only supported on PMCs 0-3:
- UOPS_DISPATCHED.INT_EU_ALL (0x1b2)
- UOPS_DISPATCHED.ALU (0x2b2)
Add explicit event constraints for these two events so scheduling does
not place them on unsupported counters.
Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: <stable@vger.kernel.org> # v7.0+
Link: https://patch.msgid.link/20260917015234.981153-10-dapeng1.mi@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/task-analyzer-record')
0 files changed, 0 insertions, 0 deletions