diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-07-23 16:41:47 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-08-31 12:20:06 +0200 |
| commit | d48a308fabd6dc7676d570f0bc971817e39d824c (patch) | |
| tree | 483a8f7a5dbbd75fea994d74705a5a5700af1748 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | cee9395acd8043be0644b25c34bfa86623f2b935 (diff) | |
| download | linux-next-d48a308fabd6dc7676d570f0bc971817e39d824c.tar.gz linux-next-d48a308fabd6dc7676d570f0bc971817e39d824c.zip | |
pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L
Add power-on control (POC) support for SD channels 1 and 2 on the RZ/G3L
SoC (r9a08g046).
Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC
register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return
SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set.
Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS() for
port PG and PH pins, dropping PIN_CFG_SOFT_PS which is inappropriate for
SD pins, and annotate them with PIN_CFG_IO_VMC_SD1 and PIN_CFG_IO_VMC_SD2
respectively.
Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0–DAT7)
with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work
correctly for those pins.
Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache to
save and restore the SD_CH2_POC register across suspend/resume cycles.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260723154154.319674-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions