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| author | Anurag <anurag@intel.com> | 2026-08-27 17:18:48 -0700 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2026-09-24 06:44:03 +0200 |
| commit | d224aacc8cf333700257fe0936f701848c2ea1b8 (patch) | |
| tree | df9323ac8059c4214092a1644065c5e141d0a08c /tools/perf/python/stackcollapse.py | |
| parent | 879519402cb5116538faf91952180f557083f9c3 (diff) | |
| download | linux-next-d224aacc8cf333700257fe0936f701848c2ea1b8.tar.gz linux-next-d224aacc8cf333700257fe0936f701848c2ea1b8.zip | |
thunderbolt: Fix sideband register access in usb4_port_sw_margin_errors()
The READ_SW_MARGIN_ERR (RDSW) completion payload is returned in the USB4
sideband data window, but the location differs between standard and
extended error counters.
Standard error counters are returned in USB4_SB_METADATA and fit within
a single dword. Extended error counters require 4 dwords and are returned
in USB4_SB_DATA.
Add conditional logic to select the appropriate register based on the
dwords parameter that corresponds with error counter type.
Co-developed-by: Rene Sapiens <rene.sapiens@linux.intel.com>
Signed-off-by: Rene Sapiens <rene.sapiens@linux.intel.com>
Signed-off-by: Anurag <anurag@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'tools/perf/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions