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| author | Prathamesh Shete <pshete@nvidia.com> | 2026-09-16 06:51:32 +0000 |
|---|---|---|
| committer | Linus Walleij <linusw@kernel.org> | 2026-09-21 00:06:32 +0200 |
| commit | ae2c5bf969573708cd5b6bb6393631255d83c3fe (patch) | |
| tree | 6a723fe3a0162937508ab6f44edc1b889a69f3a9 /tools/perf/python/stackcollapse.py | |
| parent | 447dcff90557748a5ac384aaf5d70b2c7e3b961d (diff) | |
| download | linux-next-ae2c5bf969573708cd5b6bb6393631255d83c3fe.tar.gz linux-next-ae2c5bf969573708cd5b6bb6393631255d83c3fe.zip | |
pinctrl: tegra238: Fix register bank for AON pin groups
The AON pin controller has a single register region and therefore,
the bank defined in the tegra238_functions[] and tegra238_aon_groups[]
for the AON pin groups must be 0. However, commit 25cac7292d49
("pinctrl: tegra: Add Tegra238 pinmux driver") incorrectly specified the
bank for these pins as 1 and not 0. This means that in the
tegra_pinctrl_probe() function we use an invalid index when accessing
the pmx->regs[] array which causes an incorrect address to be used for
accessing the pinmux registers.
Fix this by correcting the bank for the AON pin groups.
Fixes: 25cac7292d49 ("pinctrl: tegra: Add Tegra238 pinmux driver")
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Diffstat (limited to 'tools/perf/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions