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authorOleg Keri <okerixx@gmail.com>2026-10-09 01:07:25 +0200
committerAndi Shyti <andi.shyti@kernel.org>2026-10-10 15:36:44 +0200
commited404d9fd36b826f43e85a7c7cc77b3d966cf83d (patch)
tree590f5e77589ed97203c89cad66d2004f180bf3db /tools/lib/python
parent7109df1eafca7163f7714d287df922b4f2c104b2 (diff)
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i2c: qcom-cci: skip core clock rates the clock cannot provide
cci_get_required_rate() picks the lowest rate that has timings for every active master, but never checks that the CCI clock can run at it. On glymur, sm8750 and kaanapali the CCI clock table has no 19.2 MHz entry, so the request rounds up to 30 MHz or 37.5 MHz, the timing lookup for the running rate fails and the controller does not probe: i2c-qcom-cci ac16000.cci: CCI clock is not at expected 19200000 Hz i2c-qcom-cci ac16000.cci: no timing for mode 1 at CCI clock 30000000 Hz i2c-qcom-cci ac16000.cci: probe with driver i2c-qcom-cci failed with error -95 Only consider rates clk_round_rate() can deliver exactly. Glymur then runs its CCI at 37.5 MHz, which has timings for every mode. Fixes: fa1eb3af12fa ("i2c: qcom-cci: Enforce the required CCI clock rate") Signed-off-by: Oleg Keri <okerixx@gmail.com> Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20261008230725.3228-1-okerixx@gmail.com
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