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| author | Changhuang Liang <changhuang.liang@starfivetech.com> | 2026-08-28 02:56:01 -0700 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2026-10-02 21:17:31 +0100 |
| commit | c4a545d3e428e9600d670fa8a08098b7bc82d5ec (patch) | |
| tree | 9951074b0f911f2c5e4c3643c9bc3ee909e307df /tools/lib/python | |
| parent | 17986e31f3b6142c302c8f9af16540422787daf9 (diff) | |
| download | linux-next-c4a545d3e428e9600d670fa8a08098b7bc82d5ec.tar.gz linux-next-c4a545d3e428e9600d670fa8a08098b7bc82d5ec.zip | |
dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.
Add the PLL clocks for the sys0, per0, and per1 domains under syscon,
as well as the PCIe RP reset.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions