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| author | Hal Feng <hal.feng@starfivetech.com> | 2026-08-10 11:07:13 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2026-10-02 18:35:12 +0100 |
| commit | 2186ec5f59c23fcf0bf896ca0543b6a1135d7bb5 (patch) | |
| tree | d9f36f0341f1cf67fde88a0d8452a9d641094546 /tools/lib/python | |
| parent | f55a54f07a367ed5c73ae53398a60c01219a6df3 (diff) | |
| download | linux-next-2186ec5f59c23fcf0bf896ca0543b6a1135d7bb5.tar.gz linux-next-2186ec5f59c23fcf0bf896ca0543b6a1135d7bb5.zip | |
riscv: dts: starfive: Correct pwm nodes
Each of the StarFive JH7100/JH7110 SoCs has 8 OpenCores PTC IP
cores. One OpenCores PTC IP core can output one PWM channel.
Change the register size to 0x10, since an OpenCores PTC IP
has only 4 32-bit registers: CNTR, HRC, LRC and CTRL.
Fixes: 8d01f741a046 ("riscv: dts: starfive: jh7110: Add PWM node and pins configuration")
Fixes: 5e598b99fedf ("riscv: dts: starfive: jh7100: Add PWM node and pins configuration")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions