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| author | Yong-Xuan Wang <yongxuan.wang@sifive.com> | 2026-10-05 19:02:38 -0600 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-10-05 19:02:38 -0600 |
| commit | 148ab873d8194cb44f29474da3b4428fa2e100d1 (patch) | |
| tree | 9d787f89fd2109d1771d659bb7deb1f22d8ddd6d /tools/lib/python | |
| parent | 55b1276ef9c1c27e8a2b2c5e8ef0515b5ad0332c (diff) | |
| download | linux-next-148ab873d8194cb44f29474da3b4428fa2e100d1.tar.gz linux-next-148ab873d8194cb44f29474da3b4428fa2e100d1.zip | |
RISC-V: errata: Add SiFive MAL-9092 workaround
SiFive cores with MAL-9092 require fence.rw instructions around
HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering
when accessing guest memory.
Note that HSTATUS.HU is cleared during KVM initialization, restricting
hypervisor instructions to HS-mode only. If future changes enable
HSTATUS.HU for U-mode access, additional errata considerations will be
needed.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://patch.msgid.link/20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions