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authorLoic Poulain <loic.poulain@oss.qualcomm.com>2026-09-29 14:25:47 +0200
committerAndi Shyti <andi.shyti@kernel.org>2026-10-04 16:32:44 +0200
commit04ec5e09518b2fafe03540a0c93df858be99cefd (patch)
tree6e28dd5a9234fd1819f98f61d9ae355346acdc31 /tools/lib/python
parente2ac856c74518976c76b8736363c64a84ebbd155 (diff)
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linux-next-04ec5e09518b2fafe03540a0c93df858be99cefd.zip
i2c: qcom-cci: Add 19.2 MHz timings for the v2 CCI
The v2 CCI (msm8996/sdm630/msm8953/...) is normally clocked at 37.5 MHz, but its CCI clock can also be configured and run at 19.2 MHz. Add the Standard and Fast timing sets calibrated for 19.2 MHz so that a v2 controller left at that rate still has valid timings for those modes (Fast+ requires 37.5 MHz). The values mirror the v1/v1.5 19.2 MHz Standard/Fast timings, which share the same CCI clock rate. Note the "v1"/"v1.5"/"v2" labels are arbitrary driver-internal names for the cci_data configs, not actual CCI hardware version numbers (the real hw versions are e.g. v1.0.7 on msm8974, v1.4.0 on msm8996, v1.6.3 on sdm630/660, ...). They only distinguish the timing/mode configurations used by the driver, and will be subsequently removed. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20260929-cci-clk-fix-v6-3-62a268cccb0f@oss.qualcomm.com
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