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authorLuca Weiss <luca.weiss@fairphone.com>2026-08-07 09:46:06 +0200
committerBjorn Andersson <andersson@kernel.org>2026-08-31 15:05:31 -0500
commit0bfb542fc3368371cefb4cf45ef21c3ba2d37c3f (patch)
tree891a1b4726c62fe8bb0c50487a90e58c26c115e5 /tools/lib/python/kdoc
parent62bbf7ed9ad97c17377377aae50b7ea7feb9464e (diff)
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clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks
The critical_cbrcrs array will get qcom_branch_set_clk_en() called on each entry which will set BIT(0) to enable the clock. This is however wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set respectively to enable them. Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20260807-various-pcie-clk-fix-v1-3-5caf78a599d7@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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