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authorRyan Chen <ryan_chen@aspeedtech.com>2026-09-16 08:38:02 +0800
committerVinod Koul <vkoul@kernel.org>2026-10-05 12:04:03 +0200
commitad72aff5b4b5396a2a443a8f838fcfb8067dc603 (patch)
treed93f0024f08d72d230ea57a8cdc39e174c771235 /tools/lib/python/kdoc/python_version.py
parente22b112f2fa565fd7d2715ac9d1bc3ba1a3c2427 (diff)
downloadlinux-next-ad72aff5b4b5396a2a443a8f838fcfb8067dc603.tar.gz
linux-next-ad72aff5b4b5396a2a443a8f838fcfb8067dc603.zip
phy: aspeed: Add AST2700 USB3.2 PHY driver
Add a driver for the USB3.2 PHY on the Aspeed AST2700, which is paired with the DWC3 controller. The PHY draws its configuration from an internal SRAM in both of the available modes, so the driver must wait for PHY3S00_INIT_DONE before selecting one. PHY3S00_SRAM_BYPASS selects the default design configuration and PHY3S00_SRAM_EXT_LOAD the ROM code configuration; the driver uses the latter. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-upstream_usb3phy-v4-2-812e76037d01@aspeedtech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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