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authorChanghuang Liang <changhuang.liang@starfivetech.com>2026-08-28 02:56:07 -0700
committerConor Dooley <conor.dooley@microchip.com>2026-10-02 21:18:24 +0100
commit96b35a1251dc9977967286623fd15fcef34feeb1 (patch)
tree1dd4d7ddbb353641ee3d22c0649855c49ef41cda /tools/lib/python/kdoc/parse_data_structs.py
parentc4a545d3e428e9600d670fa8a08098b7bc82d5ec (diff)
downloadlinux-next-96b35a1251dc9977967286623fd15fcef34feeb1.tar.gz
linux-next-96b35a1251dc9977967286623fd15fcef34feeb1.zip
soc: starfive: Add socinfo driver for JHB100 SoC
Add a socinfo driver for the JHB100 SoC, exposing the SoC family, ID and revision through the SoC bus. It is currently used to distinguish the two revisions, A0 and A1. The driver binds to the sys0 system controller node. That region only contains the PLL controls, this revision ID register and a few debug registers, so rather than describing an extra child node in the devicetree, the sys0 PLL device is instantiated from here as an MFD cell. The PLL driver then picks up the regmap from its parent's DT node. Note that CONFIG_STARFIVE_JHB100_SOCINFO is therefore a build-time prerequisite for the sys0 PLL clocks; see CLK_STARFIVE_JHB100_PLL. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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