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| author | Changhuang Liang <changhuang.liang@starfivetech.com> | 2026-09-30 05:43:11 -0700 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2026-10-02 20:58:09 +0100 |
| commit | 5b86a2f9415fdf4ef1188fdfe0dafb1727328cfd (patch) | |
| tree | 098751a693a869391c9ec4f8351ef58ef785e38e /tools/lib/python/feat/parse_features.py | |
| parent | d20c33354c2234f52f426d283eaf85b1e4f375dd (diff) | |
| download | linux-next-5b86a2f9415fdf4ef1188fdfe0dafb1727328cfd.tar.gz linux-next-5b86a2f9415fdf4ef1188fdfe0dafb1727328cfd.zip | |
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
Add bindings for the Peripheral-2 clock and reset generator (PER2CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/lib/python/feat/parse_features.py')
0 files changed, 0 insertions, 0 deletions