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authorRichard Cheng <icheng@nvidia.com>2026-11-03 14:34:09 +0800
committerDave Jiang <dave.jiang@intel.com>2026-11-10 11:34:51 -0700
commited574daa568d3d4caf4c752181cbd9d41a220465 (patch)
tree8fd24848248e3295be5464cf1fecc0424223faf4 /scripts/Makefile.thinlto
parent6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 (diff)
downloadlinux-next-ed574daa568d3d4caf4c752181cbd9d41a220465.tar.gz
linux-next-ed574daa568d3d4caf4c752181cbd9d41a220465.zip
cxl/port: Fix endpoint RAS error unmasking
Moving endpoint RAS handling from cxl_pci to cxl_port left cxl_ras_unmask() checking whether port->uport_dev is a PCI device. Endpoint ports always use a cxl_memdev as uport_dev, so this check returns early and leaves the CXL RAS error masks unchanged. Resolve the PCI device directly through the memdev's parent. Rename helper to cxl_endpoint_ras_unmask() and its param to endpoint to make its endpoint-only scope explicit. Fixes: dab7162d0ae7 ("cxl/port: Move endpoint component register management to cxl_port") Signed-off-by: Richard Cheng <icheng@nvidia.com> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> Link: https://patch.msgid.link/20261103063409.18275-1-icheng@nvidia.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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