cxl/test: Add mock BI topology support

Extend the mock topology with a Back-Invalidate path
covering both the type3 memdevs and the type2 accelerator.

Following the framework's convention of substituting software state
for register programming, cxl_bi_probe_capable() gains a --wrap shim
dispatching through cxl_mock_ops, and the mock decoder setup enables
BI in software in place of cxl_bi_setup(). The mock setup mirrors
cxl_bi_enable_path()'s walk - dport nr_bi accounting up to the root,
unwound by a devm action - and the capability check keeps the
VH-only rule.

A single HDM-DB window (BI | DEVMEM | VOLATILE, targeting host
bridge 0) is emitted in every topology mode and parses into a
CXL_DECODER_F_BI root decoder; DEVMEM satisfies can_create_ram().
In type2 mode it coexists with the accelerator's HDM-D window.

Committed BI state is a decoder flag, so the mock sets
CXL_DECODER_F_BI on decoder commit and clears it on reset, and
restores it on saved-decoder replay - letting a committed HDM-DB
region survive a cxl_acpi rebind with no register to emulate.
Endpoints get a page of plain memory standing in for BI Decoder
Control, with BI Enable set, since committing an HDM-DB region reads
it back. The accelerator grows to 1G of capacity so the boot-time
auto region leaves DPA for a BI region.

Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Link: https://patch.msgid.link/8e4b3beafc0f195452ccd113c0e4f193fba58d7d.1794172701.git.dave@stgolabs.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

0 files changed, 0 insertions, 0 deletions