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| author | Davidlohr Bueso <dave@stgolabs.net> | 2026-11-08 14:07:35 -0800 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-11-09 15:25:19 -0700 |
| commit | 6b47c508bd530b6f11a5782fd0e2af5d767092d0 (patch) | |
| tree | 64294a0a7649e9cf9b22c894c3cca94ea1015e20 /scripts/Makefile.thinlto | |
| parent | 77b165a5fce04d3ad778f5f3e4a2d67e6ce8e86d (diff) | |
| download | linux-next-6b47c508bd530b6f11a5782fd0e2af5d767092d0.tar.gz linux-next-6b47c508bd530b6f11a5782fd0e2af5d767092d0.zip | |
cxl/region: Log the coherency model at region creation
Region assembly emits plenty of debug information - resources,
interleave geometry, target placement - but not the coherency model
the region operates in.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Not-Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Link: https://patch.msgid.link/14eca21bb727ebe0d8e361067bfba06a8d982b1d.1794172701.git.dave@stgolabs.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/Makefile.thinlto')
0 files changed, 0 insertions, 0 deletions