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| author | Birk Skyum <birk.skyum@pm.me> | 2026-10-21 21:04:35 +0000 |
|---|---|---|
| committer | Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> | 2026-10-28 10:25:02 +0100 |
| commit | 30d9a180c86e3cbd53efb7152e05cb059112f6eb (patch) | |
| tree | 9f04477734090a03a78bcf05a6f7fdfbfc5a277e /scripts/Makefile.thinlto | |
| parent | 9bcd1725b0cc7954525e3d0d02fecaec7c7aab33 (diff) | |
| download | linux-next-30d9a180c86e3cbd53efb7152e05cb059112f6eb.tar.gz linux-next-30d9a180c86e3cbd53efb7152e05cb059112f6eb.zip | |
pinctrl: qcom: Restore the pin configuration after hibernation
A hibernation image is restored after a power cycle. The TLMM registers
then hold what the boot firmware and the kernel that loaded the image
made of them. The restored kernel has the configuration it applied in
memory only, and nothing writes it to the hardware again, so every pin
that the loading kernel did not set up the same way stays wrong.
On a Lenovo Yoga Slim 7x (X1E80100) the Bluetooth and Wi-Fi enable lines
are two of them. Their drivers are loaded from the root file system, so
the kernel that loads the image never touches the pins. This is
/sys/kernel/debug/gpio before the hibernation and after the resume:
gpio116 : out low func0 2mA no pull
gpio117 : out high func0 2mA no pull
gpio116 : in low func0 2mA pull down
gpio117 : out high func0 16mA no pull
The driver that owns gpio116 still believes it drives the line.
Save the control, output and interrupt configuration registers in
freeze_noirq and write them back in restore_noirq, the output level
first, so that a pin drives the right level from the moment it becomes
an output. Changing the interrupt configuration can latch an interrupt,
so the configuration is written with the interrupt disabled, the status
is cleared where the register changed, as msm_gpio_irq_set_type() does
with the interrupt masked, and only then is the interrupt enabled again.
Only the GPIOs the kernel uses are put back: those requested as a GPIO,
muxed to a function or used as an interrupt, as pinctrl-intel does. A
valid GPIO without an owner may be in use by firmware. The SDC pads
after the GPIOs are configured without a mux function, so they never
have an owner, and their control register is always put back.
msm_pinctrl_dev_pm_ops gets the two callbacks and x1e80100 starts using
these ops. With that x1e80100 also gets their suspend and resume
callbacks, which apply the sleep and default state of the controller's
own pins where a board defines them.
Signed-off-by: Birk Skyum <birk.skyum@pm.me>
Link: https://patch.msgid.link/20261021210425.57066-1-birk.skyum@pm.me
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Diffstat (limited to 'scripts/Makefile.thinlto')
0 files changed, 0 insertions, 0 deletions
