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| author | Ed Tsai <ed.tsai@mediatek.com> | 2026-06-15 13:57:15 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2026-07-12 14:09:42 -0400 |
| commit | e7896d02cb4d0e6b4e97c62af669109ab809c0ca (patch) | |
| tree | 73bf372669ed52aa4e71fee33216d46e24efe8ad /include | |
| parent | dc59e4fea9d83f03bad6bddf3fa2e52491777482 (diff) | |
| download | linux-next-e7896d02cb4d0e6b4e97c62af669109ab809c0ca.tar.gz linux-next-e7896d02cb4d0e6b4e97c62af669109ab809c0ca.zip | |
scsi: ufs: core: Add get_hba_nortt callback for vendor-specific RTT capability
The number of outstanding RTTs read from host controller capability
register is problematic on some platforms. Add a new vendor callback
get_hba_nortt() to allow platform vendors to override the default RTT
capability value with platform-specific handling.
This patch keeps max_num_rtt field for bisectability and will be removed in
a later patch once all platforms are migrated.
Signed-off-by: Ed Tsai <ed.tsai@mediatek.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Link: https://patch.msgid.link/20260615055802.105479-2-ed.tsai@mediatek.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ufs/ufshcd.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 248d0a5bef40..8e24c4b8e963 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -417,6 +417,8 @@ struct ufshcd_tx_eq_params { * @get_rx_fom: called to get Figure of Merit (FOM) value. * @tx_eqtr_notify: called before and after TX Equalization Training procedure * to allow platform vendor specific configs to take place. + * @get_hba_nortt: called to get maximum number of outstanding RTTs supported by + * the controller. */ struct ufs_hba_variant_ops { const char *name; @@ -479,6 +481,7 @@ struct ufs_hba_variant_ops { int (*tx_eqtr_notify)(struct ufs_hba *hba, enum ufs_notify_change_status status, struct ufs_pa_layer_attr *pwr_mode); + int (*get_hba_nortt)(struct ufs_hba *hba); }; /* clock gating state */ |