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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-09-24 14:36:11 +0200 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-09-24 14:36:11 +0200 |
| commit | 9726f5bc5f668fa5cd045bafb374cfc6956bbc8c (patch) | |
| tree | 72c65255df4df6b5233aea3324dab4a81099dc12 /include | |
| parent | 92aaf76ee9af2bb43c6acaed36f48c1a74f17298 (diff) | |
| parent | 51c659ebdc10b1c4d1a0a83578868462ecb867f3 (diff) | |
| download | linux-next-9726f5bc5f668fa5cd045bafb374cfc6956bbc8c.tar.gz linux-next-9726f5bc5f668fa5cd045bafb374cfc6956bbc8c.zip | |
Merge branch 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm into renesas-dts-for-v7.4
PM Domain DT bindings and binding definitions for the Renesas RZ/G2M
v3.0 (R8A774A3) SoC, shared by driver and DT source files.
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/power/qcom,rpmhpd.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/power/renesas,r8a774a3-sysc.h | 30 |
2 files changed, 31 insertions, 0 deletions
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h index 07bd2a7b0150..92c8408dbc57 100644 --- a/include/dt-bindings/power/qcom,rpmhpd.h +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -32,6 +32,7 @@ #define RPMHPD_GBX 22 #define RPMHPD_NSP3 23 #define RPMHPD_GFX1 24 +#define RPMHPD_NMXC 25 /* RPMh Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 diff --git a/include/dt-bindings/power/renesas,r8a774a3-sysc.h b/include/dt-bindings/power/renesas,r8a774a3-sysc.h new file mode 100644 index 000000000000..ddee6812e9a4 --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a774a3-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774A3_PD_CA57_CPU0 0 +#define R8A774A3_PD_CA57_CPU1 1 +#define R8A774A3_PD_CA53_CPU0 5 +#define R8A774A3_PD_CA53_CPU1 6 +#define R8A774A3_PD_CA53_CPU2 7 +#define R8A774A3_PD_CA53_CPU3 8 +#define R8A774A3_PD_CA57_SCU 12 +#define R8A774A3_PD_A3VC 14 +#define R8A774A3_PD_3DG_A 17 +#define R8A774A3_PD_3DG_B 18 +#define R8A774A3_PD_CA53_SCU 21 +#define R8A774A3_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774A3_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ */ |