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| author | Mark Brown <broonie@kernel.org> | 2026-11-13 17:23:45 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-11-13 17:23:45 +0000 |
| commit | 91e174e86ee7b4c636fea03752d43aa0ded8df4e (patch) | |
| tree | ac7af2d6e5ab445c4100a968ea9a4a4e4a42a4b3 /include | |
| parent | 4507970404e9dde2a3cb6b799d36d44f03131879 (diff) | |
| parent | d4780f61df995bef6b7b97958b9f1856593740d7 (diff) | |
| download | linux-next-91e174e86ee7b4c636fea03752d43aa0ded8df4e.tar.gz linux-next-91e174e86ee7b4c636fea03752d43aa0ded8df4e.zip | |
Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git
Diffstat (limited to 'include')
| -rw-r--r-- | include/cxl/cxl.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 1c04a7823f64..6fa9d913ccdb 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -16,7 +16,8 @@ * mailbox, or other memory-device-standard manageability * flows. * @CXL_DEVTYPE_CLASSMEM: Common class definition of a CXL Type-3 device with - * HDM-H and class-mandatory memory device registers + * HDM-H or HDM-DB, and class-mandatory memory device + * registers */ enum cxl_devtype { CXL_DEVTYPE_DEVMEM, @@ -34,10 +35,14 @@ struct cxl_regs { * Common set of CXL Component register block base pointers * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure + * @bi_rt: CXL 4.0 8.2.4.26 CXL BI Route Table Capability Structure + * @bi_decoder: CXL 4.0 8.2.4.27 CXL BI Decoder Capability Structure */ struct_group_tagged(cxl_component_regs, component, void __iomem *hdm_decoder; void __iomem *ras; + void __iomem *bi_rt; + void __iomem *bi_decoder; ); /* * Common set of CXL Device register block base pointers @@ -80,6 +85,8 @@ struct cxl_reg_map { struct cxl_component_reg_map { struct cxl_reg_map hdm_decoder; struct cxl_reg_map ras; + struct cxl_reg_map bi_rt; + struct cxl_reg_map bi_decoder; }; struct cxl_device_reg_map { @@ -189,6 +196,8 @@ struct cxl_dpa_partition { * @regs: Parsed register blocks * @cxl_dvsec: Offset to the PCIe device DVSEC * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) + * @bi: device is BI (Back-Invalidate) enabled + * @bi_capable: device and topology path are BI capable * @media_ready: Indicate whether the device media is usable * @dpa_res: Overall DPA resource tree for the device * @part: DPA partition array @@ -208,6 +217,8 @@ struct cxl_dev_state { struct cxl_device_regs regs; int cxl_dvsec; bool rcd; + bool bi; + bool bi_capable; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; |