Merge branch into tip/master: 'perf/core'

# New commits in perf/core:
    6350de8671b9 ("perf/x86/amd/uncore: Free counter slot by index")
    4a8557a4e5d2 ("perf/x86/amd/uncore: Remove redundant event slot scan")
    ba29babd881e ("perf/x86/intel: Check only PMC bits in PEBS_ENABLED when detecting host PEBS usage")
    193ef44e3261 ("KVM: VMX: Only tell perf to enable PEBS counters for fully enabled PMCs")
    57c764783330 ("KVM: VMX: Drop a redundant pmu->global_ctrl check when processing pebs_enable")
    31f7cf337ce7 ("perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM")
    a634e4536ec2 ("perf/x86: KVM: Have perf define a dedicated struct for getting guest PEBS data")
    b7b84fff2bd6 ("perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask")
    52a6457f59ad ("perf/x86/intel: Annotate x86_pmu::hybrid_pmu with __counted_by_ptr")
    df935e26ca9a ("perf/x86/amd/uncore: Turn amd_uncore_ctx events into a flexible array")
    df53fbc909cd ("Merge branch 'perf/urgent' into perf/core, to resolve conflict")
    68aca309e49c ("perf/x86/intel: Add sanity check for PEBS record/fragment size")
    c34db2f95094 ("perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs")
    00cf8daabe2b ("perf/x86/intel: Advertise PERF_PMU_CAP_SIMD_REGS capability")
    c4fabb67a47f ("perf/x86/intel: Support arch-PEBS based SIMD/eGPRs sampling")
    098cdd582a9b ("perf/x86: Support SSP sampling using sample_regs_* fields")
    578460d9af8d ("perf/x86: Support eGPRs sampling using sample_regs_* fields")
    a2c64c74c029 ("perf: Enhance perf_reg_validate() with simd_enabled argument")
    74d55a827e31 ("perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields")
    3807f6996a0b ("perf/x86: Support ZMM sampling using sample_simd_vec_reg_* fields")
    b76210d32147 ("perf/x86: Support YMM sampling using sample_simd_vec_reg_* fields")
    e9d76ada769c ("perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields")
    918b7d6d1729 ("perf: Add sampling support for SIMD registers")
    edd9aec51213 ("perf/x86: Enable XMM register sampling for REGS_USER case")
    b84c96283684 ("perf/x86: Enable XMM register sampling for non-PEBS events")
    c09466807467 ("perf/x86/intel: Centralize PERF_PMU_CAP_EXTENDED_REGS updates")
    05fe8825796e ("perf: Move and enhance has_extended_regs() for arch-specific use")
    450d73dc5f91 ("x86/fpu: Add update_fpu_state_and_flag() helper")
    03b89c9f202e ("x86/fpu/xstate: Add xsaves_nmi() helper")
    9c05620b4971 ("perf/x86: Use x86_perf_regs in NMI handlers")
    cb388bd530cc ("perf: Eliminate duplicate arch-specific function definitions")
    bbdf84fcedfa ("perf/x86/intel: Convert x86_perf_regs to per-cpu variables")
    62e074f55f41 ("perf/x86/intel: Enable large PEBS sampling for XMMs")
    9106892e27ca ("perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu()")

Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 45 insertions, 4 deletions

diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index fd10aa8d697f..c49fc76292f7 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -314,8 +314,9 @@ enum {
  */
 enum perf_sample_regs_abi {
 	PERF_SAMPLE_REGS_ABI_NONE		= 0,
-	PERF_SAMPLE_REGS_ABI_32			= 1,
-	PERF_SAMPLE_REGS_ABI_64			= 2,
+	PERF_SAMPLE_REGS_ABI_32			= (1 << 0),
+	PERF_SAMPLE_REGS_ABI_64			= (1 << 1),
+	PERF_SAMPLE_REGS_ABI_SIMD		= (1 << 2),
 };
 
 /*
@@ -383,6 +384,7 @@ enum perf_event_read_format {
 #define PERF_ATTR_SIZE_VER7			128	/* Add: sig_data */
 #define PERF_ATTR_SIZE_VER8			136	/* Add: config3 */
 #define PERF_ATTR_SIZE_VER9			144	/* add: config4 */
+#define PERF_ATTR_SIZE_VER10			176	/* Add: sample_simd_{vec|pred}_reg_* */
 
 /*
  * 'struct perf_event_attr' contains various attributes that define
@@ -547,6 +549,29 @@ struct perf_event_attr {
 
 	__u64	config3; /* extension of config2 */
 	__u64	config4; /* extension of config3 */
+
+	/*
+	 * Defines the sampling SIMD/PRED(predicate) registers bitmap and
+	 * qwords (8 bytes) length.
+	 *
+	 * sample_simd_regs_enabled != 0 indicates there are SIMD/PRED
+	 * registers to be sampled, the SIMD/PRED registers bitmap and
+	 * qwords length are represented in
+	 * sample_simd_{vec|pred}_reg_{intr|user} and
+	 * sample_simd_{vec|pred}_reg_qwords fields separately.
+	 *
+	 * sample_simd_regs_enabled == 0 indicates no SIMD/PRED registers
+	 * are sampled.
+	 */
+	__u16	sample_simd_regs_enabled;
+	__u16	sample_simd_pred_reg_qwords;
+	__u16	sample_simd_vec_reg_qwords;
+	__u16	__reserved_4;
+
+	__u32	sample_simd_pred_reg_intr;
+	__u32	sample_simd_pred_reg_user;
+	__u64	sample_simd_vec_reg_intr;
+	__u64	sample_simd_vec_reg_user;
 };
 
 /*
@@ -1020,7 +1045,15 @@ enum perf_event_type {
 	 *      } && PERF_SAMPLE_BRANCH_STACK
 	 *
 	 *	{ u64			abi; # enum perf_sample_regs_abi
-	 *	  u64			regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
+	 *	  u64			regs[weight(mask)];
+	 *	  struct {
+	 *		u64 nr_vectors;		# 0 ... weight(sample_simd_vec_reg_user)
+	 *		u64 vector_qwords;	# 0 ... sample_simd_vec_reg_qwords
+	 *		u64 nr_pred;		# 0 ... weight(sample_simd_pred_reg_user)
+	 *		u64 pred_qwords;	# 0 ... sample_simd_pred_reg_qwords
+	 *		u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords];
+	 *	  } && (abi & PERF_SAMPLE_REGS_ABI_SIMD)
+	 *	} && PERF_SAMPLE_REGS_USER
 	 *
 	 *	{ u64			size;
 	 *	  char			data[size];
@@ -1047,7 +1080,15 @@ enum perf_event_type {
 	 *	{ u64			data_src; } && PERF_SAMPLE_DATA_SRC
 	 *	{ u64			transaction; } && PERF_SAMPLE_TRANSACTION
 	 *	{ u64			abi; # enum perf_sample_regs_abi
-	 *	  u64			regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
+	 *	  u64			regs[weight(mask)];
+	 *	  struct {
+	 *		u64 nr_vectors;		# 0 ... weight(sample_simd_vec_reg_intr)
+	 *		u64 vector_qwords;	# 0 ... sample_simd_vec_reg_qwords
+	 *		u64 nr_pred;		# 0 ... weight(sample_simd_pred_reg_intr)
+	 *		u64 pred_qwords;	# 0 ... sample_simd_pred_reg_qwords
+	 *		u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords];
+	 *	  } && (abi & PERF_SAMPLE_REGS_ABI_SIMD)
+	 *	} && PERF_SAMPLE_REGS_INTR
 	 *	{ u64			phys_addr;} && PERF_SAMPLE_PHYS_ADDR
 	 *	{ u64			cgroup;} && PERF_SAMPLE_CGROUP
 	 *	{ u64			data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE