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| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2023-01-19 14:27:04 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-01-23 12:44:18 +0000 |
| commit | 6505b68056558357dc979d11921ed45cfd68ed69 (patch) | |
| tree | dc4fecbc9d72af54df8bfccf7f72fe36f95e0e51 /include/soc/mscc/ocelot_dev.h | |
| parent | ab3f97a9610a8d90dc9934517e82c3272d4e98a0 (diff) | |
| download | linux-next-6505b68056558357dc979d11921ed45cfd68ed69.tar.gz linux-next-6505b68056558357dc979d11921ed45cfd68ed69.zip | |
net: mscc: ocelot: add MAC Merge layer support for VSC9959
Felix (VSC9959) has a DEV_GMII:MM_CONFIG block composed of 2 registers
(ENABLE_CONFIG and VERIF_CONFIG). Because the MAC Merge statistics and
pMAC statistics are already in the Ocelot switch lib even if just Felix
supports them, I'm adding support for the whole MAC Merge layer in the
common Ocelot library too.
There is an interrupt (shared with the PTP interrupt) which signals
changes to the MM verification state. This is done because the
preemptible traffic classes should be committed to hardware only once
the verification procedure has declared the link partner of being
capable of receiving preemptible frames.
We implement ethtool getters and setters for the MAC Merge layer state.
The "TX enabled" and "verify status" are taken from the IRQ handler,
using a mutex to ensure serialized access.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/soc/mscc/ocelot_dev.h')
| -rw-r--r-- | include/soc/mscc/ocelot_dev.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/soc/mscc/ocelot_dev.h b/include/soc/mscc/ocelot_dev.h index 0c6021f02fee..fcf02baa76b2 100644 --- a/include/soc/mscc/ocelot_dev.h +++ b/include/soc/mscc/ocelot_dev.h @@ -93,6 +93,29 @@ #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1) #define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0) +#define DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA BIT(0) +#define DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA BIT(4) +#define DEV_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D BIT(8) + +#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS BIT(0) +#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) (((x) << 4) & GENMASK(11, 4)) +#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M GENMASK(11, 4) +#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) (((x) & GENMASK(11, 4)) >> 4) +#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) (((x) << 12) & GENMASK(13, 12)) +#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M GENMASK(13, 12) +#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12) + +#define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS BIT(0) +#define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY BIT(4) +#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8)) +#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8) +#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8) +#define DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY BIT(12) +#define DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY BIT(16) +#define DEV_MM_STAT_MM_STATUS_MM_RX_FRAME_STATUS BIT(20) +#define DEV_MM_STAT_MM_STATUS_MM_TX_FRAME_STATUS BIT(24) +#define DEV_MM_STAT_MM_STATUS_MM_TX_PRMPT_STATUS BIT(28) + #define PCS1G_CFG_LINK_STATUS_TYPE BIT(4) #define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) #define PCS1G_CFG_PCS_ENA BIT(0) |
