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| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-09-18 00:25:45 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-09-28 15:42:05 -0400 |
| commit | 8c40f32361d566c0882e9d92abab36256b268291 (patch) | |
| tree | ed915aa51116a1c2b988f1a0907f865a576bda04 /include/net/aligned_data.h | |
| parent | 395280622de0c67814d8b5f06366217b3a9f70c0 (diff) | |
| download | linux-next-8c40f32361d566c0882e9d92abab36256b268291.tar.gz linux-next-8c40f32361d566c0882e9d92abab36256b268291.zip | |
arm64: dts: imx8mm-var-dart: increase PHY reset deassert delay
The Ethernet PHY reset signal also controls the regulators supplying
VDDA2P5 and VDD1P0, so releasing reset restores the PHY's 2.5 V and
1.0 V analog supplies.
The existing 100 ms reset deassertion delay is not sufficient for
reliable PHY detection. The TI DP83867 requires 200 ms of stabilization
after power-up before MDIO register access.
Increase the reset deassertion delay to 200 ms to ensure reliable PHY
detection across repeated boots.
Co-developed-by: Nate Drude <nate.d@variscite.com>
Signed-off-by: Nate Drude <nate.d@variscite.com>
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Diffstat (limited to 'include/net/aligned_data.h')
0 files changed, 0 insertions, 0 deletions