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| author | Emanuele Rocca <emanuele.rocca@arm.com> | 2026-10-05 18:21:37 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-10-08 16:45:05 -0700 |
| commit | 9142c2f8f84bf4eafe23e9d68b6ba016a60300c0 (patch) | |
| tree | 8eeb5bf1c65fdbe045b6ac9273b086e170b23526 /include/linux | |
| parent | 04a943067baa670fef3c1424ea616a2ed87d3d19 (diff) | |
| download | linux-next-9142c2f8f84bf4eafe23e9d68b6ba016a60300c0.tar.gz linux-next-9142c2f8f84bf4eafe23e9d68b6ba016a60300c0.zip | |
octeontx2: use arch_extension to enable LSE
Instead of using ".cpu generic+lse", use ".arch_extension lse" to
enable LSE.
The ".cpu generic+lse" directive replaces the assembler's current feature
set with generic+lse, dropping other previously enabled features. In
contrast, ".arch_extension lse" enables LSE while preserving the current
feature set.
For example, the following code is rejected with "selected processor does
not support retaa", because ".cpu generic+lse" drops PAuth even though it
was enabled by armv9-a:
.arch armv9-a
.text
.cpu generic+lse
retaa
We encountered this issue while building the kernel with GCC configured
using --with-arch=armv9-a. Since Armv9-A includes pointer authentication,
GCC can assume that PAuth instructions are available and may use retaa
when generating PAuth-protected returns.
Signed-off-by: Emanuele Rocca <emanuele.rocca@arm.com>
Link: https://patch.msgid.link/20261005162137.71397-1-emanuele.rocca@arm.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/soc/marvell/octeontx2/asm.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/linux/soc/marvell/octeontx2/asm.h b/include/linux/soc/marvell/octeontx2/asm.h index d683251a0b40..8b572d3d741c 100644 --- a/include/linux/soc/marvell/octeontx2/asm.h +++ b/include/linux/soc/marvell/octeontx2/asm.h @@ -17,7 +17,7 @@ #define otx2_lmt_flush(ioaddr) \ ({ \ u64 result = 0; \ - __asm__ volatile(".cpu generic+lse\n" \ + __asm__ volatile(".arch_extension lse\n" \ "ldeor xzr, %x[rf], [%[rs]]" \ : [rf]"=r" (result) \ : [rs]"r" (ioaddr)); \ @@ -30,7 +30,7 @@ */ #define cn10k_lmt_flush(val, addr) \ ({ \ - __asm__ volatile(".cpu generic+lse\n" \ + __asm__ volatile(".arch_extension lse\n" \ "steorl %x[rf],[%[rs]]" \ : [rf] "+r"(val) \ : [rs] "r"(addr)); \ @@ -40,7 +40,7 @@ static inline u64 otx2_atomic64_fetch_add(u64 incr, u64 *ptr) { u64 result; - asm volatile (".cpu generic+lse\n" + asm volatile (".arch_extension lse\n" "ldadda %x[i], %x[r], [%[b]]" : [r] "=r" (result), "+m" (*ptr) : [i] "r" (incr), [b] "r" (ptr) |