Merge tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
 "The SoC driver changes once more consist of many small fixes and
  cleanups, that are to a large part the result of automated testing.

  On platform specific drivers, this includes SoC specific code for
  xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung,
  rockchip, renesas, ixp4xx. In firmware drivers, we see a similar
  picture for SCMI and qcomtee.

  Aside from these, we see actual new hardware support in a few areas:

   - The Apple platform gets a new driver for low power states

   - Updates to Qualcomm platform drivers add several new hardware
     specific features and additional SoCs.

   - Amlogic SoC support for A1 and T7 is added

   - The Mediatek MMSYS driver is refactored as a cleanup"

* tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits)
  soc: qcom: make QCOM_PDR_MSG selectable
  soc: qcom: ubwc: Fix missing include
  soc: qcom: ubwc: Fix link error when QCOM_SMEM=n
  media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
  drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
  dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850
  firmware: xilinx: Clear firmware notifiers across kexec transitions
  firmware: xilinx: Release all peripheral devices from firmware
  firmware: xilinx: Add support to clear EL3 PM state
  firmware: xilinx: Propagate actual error from feature check
  firmware: xilinx: Use TF-A feature check for TF-A-specific APIs
  bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data
  soc: fsl: qe: check platform_driver_register() in qe_ic_of_init()
  phy: lynx-10g: use RCW override procedure for dynamic protocol change
  soc: fsl: guts: implement the RCW override procedure
  dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
  soc: fsl: guts: make fsl_soc_data available after fsl_guts_init()
  soc: fsl: guts: make it easier to determine on which SoC we are running
  soc: fsl: guts: add a central fsl_guts_read() function
  soc: fsl: guts: add a global structure to hold state
  ...

1 files changed, 43 insertions, 0 deletions

diff --git a/include/linux/firmware/qcom/qcom_pas.h b/include/linux/firmware/qcom/qcom_pas.h
new file mode 100644
index 000000000000..65b1c9564458
--- /dev/null
+++ b/include/linux/firmware/qcom/qcom_pas.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __QCOM_PAS_H
+#define __QCOM_PAS_H
+
+#include <linux/err.h>
+#include <linux/types.h>
+
+struct qcom_pas_context {
+	struct device *dev;
+	u32 pas_id;
+	phys_addr_t mem_phys;
+	size_t mem_size;
+	void *ptr;
+	dma_addr_t phys;
+	ssize_t size;
+	bool use_tzmem;
+};
+
+bool qcom_pas_is_available(void);
+struct qcom_pas_context *devm_qcom_pas_context_alloc(struct device *dev,
+						     u32 pas_id,
+						     phys_addr_t mem_phys,
+						     size_t mem_size);
+int qcom_pas_init_image(u32 pas_id, const void *metadata, size_t size,
+			struct qcom_pas_context *ctx);
+struct resource_table *qcom_pas_get_rsc_table(struct qcom_pas_context *ctx,
+					      void *input_rt, size_t input_rt_size,
+					      size_t *output_rt_size);
+int qcom_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size);
+int qcom_pas_auth_and_reset(u32 pas_id);
+int qcom_pas_prepare_and_auth_reset(struct qcom_pas_context *ctx);
+int qcom_pas_set_remote_state(u32 state, u32 pas_id);
+int qcom_pas_shutdown(u32 pas_id);
+bool qcom_pas_supported(u32 pas_id);
+void qcom_pas_metadata_release(struct qcom_pas_context *ctx);
+
+#endif /* __QCOM_PAS_H */