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| author | Imre Deak <imre.deak@intel.com> | 2026-07-14 18:26:55 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2026-07-20 15:46:08 +0300 |
| commit | b0b6d44646dc7750df4f052d17688fb7e7569a74 (patch) | |
| tree | 721c3cb52f967435ce08d895245577b8ccbb6209 /include/drm | |
| parent | 7d594b24c915afb4b0c5fb8875403253daef5b24 (diff) | |
| download | linux-next-b0b6d44646dc7750df4f052d17688fb7e7569a74.tar.gz linux-next-b0b6d44646dc7750df4f052d17688fb7e7569a74.zip | |
drm/dp_tunnel: Add UHBR tunneling support
Add the DPCD registers and detection required to support UHBR link rates
over Thunderbolt tunnels.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260714152700.555527-2-imre.deak@intel.com
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/display/drm_dp.h | 12 | ||||
| -rw-r--r-- | include/drm/display/drm_dp_tunnel.h | 21 |
2 files changed, 33 insertions, 0 deletions
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 829e4d98d61c..8a827ed0b77c 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1497,6 +1497,18 @@ #define DP_TUNNELING_MAX_LANE_COUNT 0xe0029 #define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f +#define DP_TUNNELING_MAIN_LINK_CHANNEL_CODING 0xe002b +#define DP_128B132B_DP_SUPPORTED (1 << 0) + +#define DP_TUNNELING_128B132B_LINK_RATE 0xe002c +#define DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT (1 << 2) +#define DP_TUNNELING_20GBPS_PER_LANE_SUPPORT (1 << 1) +#define DP_TUNNELING_10GBPS_PER_LANE_SUPPORT (1 << 0) +#define DP_TUNNELING_128B132B_LINK_RATE_MASK (DP_TUNNELING_10GBPS_PER_LANE_SUPPORT | \ + DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT | \ + DP_TUNNELING_20GBPS_PER_LANE_SUPPORT) +#define DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT (1 << 7) + #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030 #define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7) #define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6) diff --git a/include/drm/display/drm_dp_tunnel.h b/include/drm/display/drm_dp_tunnel.h index 57f5e90ba8fd..b5e665560a47 100644 --- a/include/drm/display/drm_dp_tunnel.h +++ b/include/drm/display/drm_dp_tunnel.h @@ -63,6 +63,9 @@ void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr, struct drm_dp_aux *aux); +bool drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel); +bool drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel); +u8 drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel); @@ -173,6 +176,24 @@ drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr, return -EOPNOTSUPP; } +static inline bool +drm_dp_tunnel_128b132b_supported(const struct drm_dp_tunnel *tunnel) +{ + return false; +} + +static inline bool +drm_dp_tunnel_128b132b_lane0_mapping_supported(const struct drm_dp_tunnel *tunnel) +{ + return false; +} + +static inline u8 +drm_dp_tunnel_128b132b_dprx_rates(const struct drm_dp_tunnel *tunnel) +{ + return 0; +} + static inline int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel) { |