ACPI: CPPC: Reject unsafe cross-CPU SystemMemory RMW

A SystemMemory CPPC field narrower than its access unit needs a
read-modify-write operation. The per-CPC-descriptor lock cannot serialize
access units described by different processors, so concurrent writers can
lose updates. _PSD domains do not define physical register ownership.

Track SystemMemory access units in a probe-time interval tree and reject
cross-descriptor partial writers sharing an access unit. Allow exact
aliases only for aligned native-width accesses to the same logical field.
Reject overlapping writable logical fields and full-width writes which
would overwrite another field. Disjoint read-only fields may share a larger
read access unit with a writer.

Within one descriptor, mark both overlapping accesses for the RMW lock,
including a full-width byte beside a wider partial field. Count only
controls written by the CPPC library as competing writers, so the unused
OSPM Nominal Performance control does not trigger a writer conflict.

Mark successful relaxed MMIO writes pending before releasing the raw
spinlock. On architectures which need an MMIO write barrier during lock
handoff, raw_spin_unlock_irqrestore() then orders the write before the next
writer enters the RMW critical section.

Validate the GAS geometry and supported access widths. Require natural
alignment where the architecture's MMIO accessors need it. Exact writable
aliases require alignment on x86 too, because an unaligned instruction need
not be one indivisible device transaction.

Keep validation results separate from the probe return value, so a
successful geometry check cannot make a later mapping failure return
success. Remove the interval records during teardown and probe rollback.

Fixes: 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com
Link: https://sashiko.dev/#/patchset/20260807111303.1062391-1-christian-loehle%40arm.com
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
Tested-by: Sumit Gupta <sumitg@nvidia.com>
Link: https://patch.msgid.link/20260916162805.1039247-9-christian.loehle@arm.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

1 files changed, 4 insertions, 1 deletions

diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index edf0f6ffb437..737219761c52 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -77,6 +77,8 @@ struct cpc_register_resource {
 	} cpc_entry;
 };
 
+struct cpc_sysmem_node;
+
 /* Container to hold the CPC details for each CPU */
 struct cpc_desc {
 	int num_entries;
@@ -84,10 +86,11 @@ struct cpc_desc {
 	int cpu_id;
 	int write_cmd_status;
 	int write_cmd_id;
-	/* Lock used for RMW operations in cpc_write() */
+	/* Serialize partial SystemMemory writes within this descriptor. */
 	raw_spinlock_t rmw_lock;
 	struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
 	struct acpi_psd_package domain_info;
+	struct cpc_sysmem_node *sysmem_nodes;
 	struct kobject kobj;
 };