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| author | Yu Zhang <zhangyu1@linux.microsoft.com> | 2026-09-30 22:14:07 +0800 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2026-10-09 10:37:41 +0200 |
| commit | 07f8807ca978f486243e93aa4e85d20df871cd7f (patch) | |
| tree | ab68ffde6a948d98094ec82f902fb3eef5b6efb2 /drivers | |
| parent | 118bdac1054628c04c547c2c988bb06ca43677a3 (diff) | |
| download | linux-next-07f8807ca978f486243e93aa4e85d20df871cd7f.tar.gz linux-next-07f8807ca978f486243e93aa4e85d20df871cd7f.zip | |
iommu/x86: Add architectural MSI reserved region helper
Intel and AMD IOMMU drivers both reserve the x86 architectural MSI
address window from normal IOVA mappings, but each open-codes the range,
allocation attributes, and insertion into the reserved-region list.
Add iommu_add_resv_x86_msi_region() to encapsulate those operations, and
convert the Intel and AMD drivers to use it. Return an error on allocation
failure so callers can preserve their existing error paths.
Signed-off-by: Yu Zhang <zhangyu1@linux.microsoft.com>
Reviewed-by: Michael Kelley <mhklinux@outlook.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/iommu/amd/iommu.c | 8 | ||||
| -rw-r--r-- | drivers/iommu/intel/iommu.c | 11 |
2 files changed, 3 insertions, 16 deletions
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 56262f6b1f70..391cec4d86c0 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -50,8 +50,6 @@ #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) /* Reserved IOVA ranges */ -#define MSI_RANGE_START (0xfee00000) -#define MSI_RANGE_END (0xfeefffff) #define HT_RANGE_START (0xfd00000000ULL) #define HT_RANGE_END (0xffffffffffULL) @@ -3137,12 +3135,8 @@ static void amd_iommu_get_resv_regions(struct device *dev, list_add_tail(®ion->list, head); } - region = iommu_alloc_resv_region(MSI_RANGE_START, - MSI_RANGE_END - MSI_RANGE_START + 1, - 0, IOMMU_RESV_MSI, GFP_KERNEL); - if (!region) + if (iommu_add_resv_x86_msi_region(head)) return; - list_add_tail(®ion->list, head); if (amd_iommu_ht_range_ignore()) return; diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2e3b3ab216f8..74fb5c894fe5 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -39,8 +39,6 @@ #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) -#define IOAPIC_RANGE_START (0xfee00000) -#define IOAPIC_RANGE_END (0xfeefffff) #define IOVA_START_ADDR (0x1000) #define DEFAULT_DOMAIN_ADDRESS_WIDTH 57 @@ -3412,7 +3410,6 @@ static void intel_iommu_get_resv_regions(struct device *device, struct list_head *head) { int prot = DMA_PTE_READ | DMA_PTE_WRITE; - struct iommu_resv_region *reg; struct dmar_rmrr_unit *rmrr; struct device *i_dev; int i; @@ -3448,6 +3445,7 @@ static void intel_iommu_get_resv_regions(struct device *device, #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA if (dev_is_pci(device)) { struct pci_dev *pdev = to_pci_dev(device); + struct iommu_resv_region *reg; if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) { reg = iommu_alloc_resv_region(0, 1UL << 24, prot, @@ -3459,12 +3457,7 @@ static void intel_iommu_get_resv_regions(struct device *device, } #endif /* CONFIG_INTEL_IOMMU_FLOPPY_WA */ - reg = iommu_alloc_resv_region(IOAPIC_RANGE_START, - IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1, - 0, IOMMU_RESV_MSI, GFP_KERNEL); - if (!reg) - return; - list_add_tail(®->list, head); + iommu_add_resv_x86_msi_region(head); } static struct iommu_group *intel_iommu_device_group(struct device *dev) |